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Searched refs:writel_bits_relaxed (Results 1 – 16 of 16) sorted by relevance

/Linux-v6.6/drivers/gpu/drm/meson/
Dmeson_viu.c105 writel_bits_relaxed(BIT(0), csc_on ? BIT(0) : 0, in meson_viu_set_g12a_osd1_matrix()
149 writel_bits_relaxed(3 << 30, m[21] << 30, in meson_viu_set_osd_matrix()
151 writel_bits_relaxed(7 << 16, m[22] << 16, in meson_viu_set_osd_matrix()
155 writel_bits_relaxed(BIT(0), csc_on ? BIT(0) : 0, in meson_viu_set_osd_matrix()
157 writel_bits_relaxed(BIT(1), 0, in meson_viu_set_osd_matrix()
168 writel_bits_relaxed(BIT(30), csc_on ? BIT(30) : 0, in meson_viu_set_osd_matrix()
170 writel_bits_relaxed(BIT(31), csc_on ? BIT(31) : 0, in meson_viu_set_osd_matrix()
221 writel_bits_relaxed(0x7 << 29, 7 << 29, in meson_viu_set_osd_lut()
224 writel_bits_relaxed(0x7 << 29, 0, in meson_viu_set_osd_lut()
248 writel_bits_relaxed(7 << 27, 7 << 27, in meson_viu_set_osd_lut()
[all …]
Dmeson_vpp.c97 writel_bits_relaxed(0xff << 16, 0xff << 16, in meson_vpp_init()
113 writel_bits_relaxed(VPP_OFIFO_SIZE_MASK, 0x77f, in meson_vpp_init()
120 writel_bits_relaxed(VPP_PREBLEND_ENABLE, 0, in meson_vpp_init()
124 writel_bits_relaxed(VPP_POSTBLEND_ENABLE, 0, in meson_vpp_init()
128 writel_bits_relaxed(VPP_OSD1_POSTBLEND | VPP_OSD2_POSTBLEND | in meson_vpp_init()
Dmeson_rdma.c65 writel_bits_relaxed(RDMA_ACCESS_RW_FLAG_CHAN1 | in meson_rdma_setup()
73 writel_bits_relaxed(RDMA_IRQ_CLEAR_CHAN1, in meson_rdma_stop()
78 writel_bits_relaxed(RDMA_ACCESS_TRIGGER_CHAN1, in meson_rdma_stop()
129 writel_bits_relaxed(RDMA_ACCESS_TRIGGER_CHAN1, in meson_rdma_flush()
Dmeson_encoder_dsi.c73 writel_bits_relaxed(ENCL_VIDEO_MODE_ADV_VFIFO_EN, ENCL_VIDEO_MODE_ADV_VFIFO_EN, in meson_encoder_dsi_atomic_enable()
77 writel_bits_relaxed(BIT(0), 0, priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_EN_CTRL)); in meson_encoder_dsi_atomic_enable()
91 writel_bits_relaxed(BIT(0), BIT(0), priv->io_base + _REG(VPP_WRAP_OSD1_MATRIX_EN_CTRL)); in meson_encoder_dsi_atomic_disable()
Dmeson_crtc.c142 writel_bits_relaxed(VPP_POSTBLEND_ENABLE, VPP_POSTBLEND_ENABLE, in meson_crtc_atomic_enable()
190 writel_bits_relaxed(VPP_OSD1_POSTBLEND | VPP_VD1_POSTBLEND | in meson_crtc_atomic_disable()
245 writel_bits_relaxed(VPP_OSD1_POSTBLEND, VPP_OSD1_POSTBLEND, in meson_crtc_enable_osd1()
254 writel_bits_relaxed(OSD_MEM_LINEAR_ADDR, OSD_MEM_LINEAR_ADDR, in meson_crtc_g12a_enable_osd1_afbc()
262 writel_bits_relaxed(OSD_MEM_LINEAR_ADDR, OSD_MEM_LINEAR_ADDR, in meson_crtc_g12a_enable_osd1_afbc()
265 writel_bits_relaxed(OSD_MALI_SRC_EN, OSD_MALI_SRC_EN, in meson_crtc_g12a_enable_osd1_afbc()
283 writel_bits_relaxed(3 << 8, 3 << 8, in meson_g12a_crtc_enable_osd1()
289 writel_bits_relaxed(VPP_VD1_PREBLEND | VPP_VD1_POSTBLEND | in meson_crtc_enable_vd1()
295 writel_bits_relaxed(VIU_CTRL0_AFBC_TO_VD1, in meson_crtc_enable_vd1()
Dmeson_dw_hdmi.c461 writel_bits_relaxed(0x3, 0, in dw_hdmi_phy_init()
463 writel_bits_relaxed(0xf << 8, 0, in dw_hdmi_phy_init()
473 writel_bits_relaxed(0xf << 8, wr_clk & (0xf << 8), in dw_hdmi_phy_init()
478 writel_bits_relaxed(0x3, MESON_VENC_SOURCE_ENCI, in dw_hdmi_phy_init()
481 writel_bits_relaxed(0x3, MESON_VENC_SOURCE_ENCP, in dw_hdmi_phy_init()
644 writel_bits_relaxed(BIT(15), BIT(15), in meson_dw_hdmi_init()
646 writel_bits_relaxed(BIT(15), BIT(15), in meson_dw_hdmi_init()
Dmeson_dw_mipi_dsi.c57 writel_bits_relaxed(MIPI_DSI_TOP_SW_RESET_DWC | MIPI_DSI_TOP_SW_RESET_INTR | in meson_dw_mipi_dsi_hw_init()
62 writel_bits_relaxed(MIPI_DSI_TOP_SW_RESET_DWC | MIPI_DSI_TOP_SW_RESET_INTR | in meson_dw_mipi_dsi_hw_init()
67 writel_bits_relaxed(MIPI_DSI_TOP_CLK_SYSCLK_EN | MIPI_DSI_TOP_CLK_PIXCLK_EN, in meson_dw_mipi_dsi_hw_init()
Dmeson_osd_afbcd.c112 writel_bits_relaxed(OSD1_AFBCD_DEC_ENABLE, 0, in meson_gxm_afbcd_disable()
301 writel_bits_relaxed(MALI_AFBCD_MANUAL_RESET, MALI_AFBCD_MANUAL_RESET, in meson_g12a_afbcd_init()
335 writel_bits_relaxed(VPU_MAFBC_S0_ENABLE, 0, in meson_g12a_afbcd_disable()
Dmeson_venc.c1045 writel_bits_relaxed(0xff, 0xff, in meson_venc_hdmi_mode_set()
1400 writel_bits_relaxed(ENCP_VIDEO_MODE_DE_V_HIGH, in meson_venc_hdmi_mode_set()
1587 writel_bits_relaxed(L_GAMMA_CNTL_PORT_EN, 0, in meson_encl_set_gamma_table()
1625 writel_bits_relaxed(L_GAMMA_CNTL_PORT_EN, L_GAMMA_CNTL_PORT_EN, in meson_encl_load_gamma()
1691 writel_bits_relaxed(ENCL_VIDEO_MODE_ADV_VFIFO_EN, 0, in meson_venc_mipi_dsi_mode_set()
1987 writel_bits_relaxed(VPU_HDMI_ENCI_DATA_TO_HDMI | in meson_venc_init()
Dmeson_plane.c412 writel_bits_relaxed(VIU_OSD1_POSTBLD_SRC_OSD1, 0, in meson_plane_atomic_disable()
415 writel_bits_relaxed(VPP_OSD1_POSTBLEND, 0, in meson_plane_atomic_disable()
Dmeson_encoder_cvbs.c177 writel_bits_relaxed(VENC_VDAC_SEL_ATV_DMD, 0, in meson_encoder_cvbs_atomic_enable()
Dmeson_encoder_hdmi.c258 writel_bits_relaxed(0x3, 0, in meson_encoder_hdmi_atomic_disable()
Dmeson_overlay.c742 writel_bits_relaxed(VPP_VD1_POSTBLEND | VPP_VD1_PREBLEND, 0, in meson_overlay_atomic_disable()
Dmeson_registers.h14 #define writel_bits_relaxed(mask, val, addr) \ macro
/Linux-v6.6/drivers/spi/
Dspi-meson-spicc.c141 #define writel_bits_relaxed(mask, val, addr) \ macro
281 writel_bits_relaxed(SPICC_BURSTLENGTH_MASK, in meson_spicc_setup_burst()
294 writel_bits_relaxed(SPICC_TC, SPICC_TC, spicc->base + SPICC_STATREG); in meson_spicc_irq()
312 writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG); in meson_spicc_irq()
387 writel_bits_relaxed(SPICC_ENH_MAIN_CLK_AO, in meson_spicc_reset_fifo()
391 writel_bits_relaxed(SPICC_FIFORST_W1_MASK, SPICC_FIFORST_W1_MASK, in meson_spicc_reset_fifo()
398 writel_bits_relaxed(SPICC_ENH_MAIN_CLK_AO, 0, in meson_spicc_reset_fifo()
446 writel_bits_relaxed(SPICC_XCH, SPICC_XCH, spicc->base + SPICC_CONREG); in meson_spicc_transfer_one()
517 writel_bits_relaxed(SPICC_LBC_W1, 0, spicc->base + SPICC_TESTREG); in meson_spicc_prepare_message()
/Linux-v6.6/drivers/media/cec/platform/meson/
Dao-cec.c228 #define writel_bits_relaxed(mask, val, addr) \ macro
309 writel_bits_relaxed(cfg, enable ? cfg : 0, in meson_ao_cec_irq_setup()
550 writel_bits_relaxed(CEC_GEN_CNTL_RESET, CEC_GEN_CNTL_RESET, in meson_ao_cec_adap_enable()
557 writel_bits_relaxed(CEC_GEN_CNTL_CLK_CTRL_MASK, in meson_ao_cec_adap_enable()
565 writel_bits_relaxed(CEC_GEN_CNTL_RESET, 0, in meson_ao_cec_adap_enable()