| /Linux-v6.6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| D | rn_clk_mgr.h | 33 extern struct wm_table ddr4_wm_table_gs;
34 extern struct wm_table lpddr4_wm_table_gs;
35 extern struct wm_table lpddr4_wm_table_with_disabled_ppt;
36 extern struct wm_table ddr4_wm_table_rn;
37 extern struct wm_table ddr4_1R_wm_table_rn;
38 extern struct wm_table lpddr4_wm_table_rn;
|
| D | rn_clk_mgr.c | 462 if (!bw_params->wm_table.entries[i].valid) in build_watermark_ranges()
465 ranges->reader_wm_sets[num_valid_sets].wm_inst = bw_params->wm_table.entries[i].wm_inst; in build_watermark_ranges()
466 ranges->reader_wm_sets[num_valid_sets].wm_type = bw_params->wm_table.entries[i].wm_type; in build_watermark_ranges()
677 bw_params->wm_table.entries[i].wm_inst = i; in rn_clk_mgr_helper_populate_bw_params()
680 bw_params->wm_table.entries[i].valid = false; in rn_clk_mgr_helper_populate_bw_params()
684 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; in rn_clk_mgr_helper_populate_bw_params()
685 bw_params->wm_table.entries[i].valid = true; in rn_clk_mgr_helper_populate_bw_params()
745 rn_bw_params.wm_table = lpddr4_wm_table_with_disabled_ppt; in rn_clk_mgr_construct()
748 rn_bw_params.wm_table = lpddr4_wm_table_gs; in rn_clk_mgr_construct()
750 rn_bw_params.wm_table = lpddr4_wm_table_rn; in rn_clk_mgr_construct()
[all …]
|
| /Linux-v6.6/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| D | dcn30_fpu.c | 370 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid) { in dcn30_fpu_update_soc_for_wm_a()
373 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries… in dcn30_fpu_update_soc_for_wm_a()
374 …context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[W… in dcn30_fpu_update_soc_for_wm_a()
375 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_A].dml_in… in dcn30_fpu_update_soc_for_wm_a()
413 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries… in dcn30_fpu_calculate_wm_and_dlg()
432 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].valid) { in dcn30_fpu_calculate_wm_and_dlg()
437 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.nv_entries… in dcn30_fpu_calculate_wm_and_dlg()
438 …context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[W… in dcn30_fpu_calculate_wm_and_dlg()
439 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.nv_entries[WM_B].dml_in… in dcn30_fpu_calculate_wm_and_dlg()
479 if (dc->clk_mgr->bw_params->wm_table.nv_entries[WM_C].valid) { in dcn30_fpu_calculate_wm_and_dlg()
[all …]
|
| /Linux-v6.6/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| D | dcn32_fpu.c | 190 …clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = dcfclk_mhz_for_the_… in dcn32_build_wm_range_table_fpu()
192 …clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = clk_mgr->base.bw_pa… in dcn32_build_wm_range_table_fpu()
198 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].valid = true; in dcn32_build_wm_range_table_fpu()
199 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.pstate_latency_us = pstate_latency_us; in dcn32_build_wm_range_table_fpu()
200 …clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.fclk_change_latency_us = fclk_change_… in dcn32_build_wm_range_table_fpu()
201 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_exit_time_us = sr_exit_time_us; in dcn32_build_wm_range_table_fpu()
202 …clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].dml_input.sr_enter_plus_exit_time_us = sr_enter… in dcn32_build_wm_range_table_fpu()
203 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE; in dcn32_build_wm_range_table_fpu()
204 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz; in dcn32_build_wm_range_table_fpu()
205 clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF; in dcn32_build_wm_range_table_fpu()
[all …]
|
| /Linux-v6.6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/ |
| D | dcn316_clk_mgr.c | 260 static struct wm_table ddr4_wm_table = {
297 static struct wm_table lpddr5_wm_table = {
346 if (!bw_params->wm_table.entries[i].valid) in dcn316_build_watermark_ranges()
349 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; in dcn316_build_watermark_ranges()
350 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; in dcn316_build_watermark_ranges()
542 bw_params->wm_table.entries[i].wm_inst = i; in dcn316_clk_mgr_helper_populate_bw_params()
545 bw_params->wm_table.entries[i].valid = false; in dcn316_clk_mgr_helper_populate_bw_params()
549 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; in dcn316_clk_mgr_helper_populate_bw_params()
550 bw_params->wm_table.entries[i].valid = true; in dcn316_clk_mgr_helper_populate_bw_params()
629 dcn316_bw_params.wm_table = lpddr5_wm_table; in dcn316_clk_mgr_construct()
[all …]
|
| /Linux-v6.6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| D | vg_clk_mgr.h | 32 extern struct wm_table ddr4_wm_table;
33 extern struct wm_table lpddr5_wm_table;
|
| D | vg_clk_mgr.c | 394 if (!bw_params->wm_table.entries[i].valid) in vg_build_watermark_ranges()
397 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; in vg_build_watermark_ranges()
398 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; in vg_build_watermark_ranges()
601 bw_params->wm_table.entries[i].wm_inst = i; in vg_clk_mgr_helper_populate_bw_params()
604 bw_params->wm_table.entries[i].valid = false; in vg_clk_mgr_helper_populate_bw_params()
608 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; in vg_clk_mgr_helper_populate_bw_params()
609 bw_params->wm_table.entries[i].valid = true; in vg_clk_mgr_helper_populate_bw_params()
718 vg_bw_params.wm_table = lpddr5_wm_table; in vg_clk_mgr_construct()
720 vg_bw_params.wm_table = ddr4_wm_table; in vg_clk_mgr_construct()
|
| /Linux-v6.6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/ |
| D | dcn31_clk_mgr.c | 343 static struct wm_table ddr5_wm_table = {
380 static struct wm_table lpddr5_wm_table = {
429 if (!bw_params->wm_table.entries[i].valid) in dcn31_build_watermark_ranges()
432 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; in dcn31_build_watermark_ranges()
433 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; in dcn31_build_watermark_ranges()
619 bw_params->wm_table.entries[i].wm_inst = i; in dcn31_clk_mgr_helper_populate_bw_params()
622 bw_params->wm_table.entries[i].valid = false; in dcn31_clk_mgr_helper_populate_bw_params()
626 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; in dcn31_clk_mgr_helper_populate_bw_params()
627 bw_params->wm_table.entries[i].valid = true; in dcn31_clk_mgr_helper_populate_bw_params()
727 dcn31_bw_params.wm_table = lpddr5_wm_table; in dcn31_clk_mgr_construct()
[all …]
|
| /Linux-v6.6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/ |
| D | dcn315_clk_mgr.c | 295 static struct wm_table ddr5_wm_table = {
332 static struct wm_table lpddr5_wm_table = {
381 if (!bw_params->wm_table.entries[i].valid) in dcn315_build_watermark_ranges()
384 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; in dcn315_build_watermark_ranges()
385 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; in dcn315_build_watermark_ranges()
564 bw_params->wm_table.entries[i].wm_inst = i; in dcn315_clk_mgr_helper_populate_bw_params()
567 bw_params->wm_table.entries[i].valid = false; in dcn315_clk_mgr_helper_populate_bw_params()
571 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; in dcn315_clk_mgr_helper_populate_bw_params()
572 bw_params->wm_table.entries[i].valid = true; in dcn315_clk_mgr_helper_populate_bw_params()
647 dcn315_bw_params.wm_table = lpddr5_wm_table; in dcn315_clk_mgr_construct()
[all …]
|
| /Linux-v6.6/drivers/gpu/drm/amd/display/dc/dml/dcn301/ |
| D | dcn301_fpu.c | 218 struct wm_table ddr4_wm_table = {
255 struct wm_table lpddr5_wm_table = {
429 table_entry = &bw_params->wm_table.entries[WM_D]; in dcn301_calculate_wm_and_dlg_fp()
437 table_entry = &bw_params->wm_table.entries[WM_C]; in dcn301_calculate_wm_and_dlg_fp()
442 table_entry = &bw_params->wm_table.entries[WM_B]; in dcn301_calculate_wm_and_dlg_fp()
448 table_entry = &bw_params->wm_table.entries[WM_A]; in dcn301_calculate_wm_and_dlg_fp()
|
| /Linux-v6.6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/ |
| D | dcn314_clk_mgr.c | 361 static struct wm_table ddr5_wm_table = {
398 static struct wm_table lpddr5_wm_table = {
447 if (!bw_params->wm_table.entries[i].valid) in dcn314_build_watermark_ranges()
450 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst; in dcn314_build_watermark_ranges()
451 table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type; in dcn314_build_watermark_ranges()
695 bw_params->wm_table.entries[i].wm_inst = i; in dcn314_clk_mgr_helper_populate_bw_params()
698 bw_params->wm_table.entries[i].valid = false; in dcn314_clk_mgr_helper_populate_bw_params()
702 bw_params->wm_table.entries[i].wm_type = WM_TYPE_PSTATE_CHG; in dcn314_clk_mgr_helper_populate_bw_params()
703 bw_params->wm_table.entries[i].valid = true; in dcn314_clk_mgr_helper_populate_bw_params()
774 dcn314_bw_params.wm_table = lpddr5_wm_table; in dcn314_clk_mgr_construct()
[all …]
|
| /Linux-v6.6/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| D | clk_mgr.h | 215 struct wm_table { struct
235 struct wm_table wm_table; member
|
| /Linux-v6.6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/ |
| D | dcn30_clk_mgr.c | 340 if (clk_mgr->base.bw_params->wm_table.nv_entries[i].valid) { in dcn3_notify_wm_ranges()
341 …table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MinClock = clk_mgr->base.bw_params->wm_table.nv_entr… in dcn3_notify_wm_ranges()
342 …table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MaxClock = clk_mgr->base.bw_params->wm_table.nv_entr… in dcn3_notify_wm_ranges()
343 …table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MinUclk = clk_mgr->base.bw_params->wm_table.nv_entri… in dcn3_notify_wm_ranges()
344 …table->Watermarks.WatermarkRow[WM_DCEFCLK][i].MaxUclk = clk_mgr->base.bw_params->wm_table.nv_entri… in dcn3_notify_wm_ranges()
346 …table->Watermarks.WatermarkRow[WM_DCEFCLK][i].Flags = clk_mgr->base.bw_params->wm_table.nv_entries… in dcn3_notify_wm_ranges()
|
| /Linux-v6.6/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| D | dcn31_fpu.c | 456 if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) { in dcn31_update_soc_for_wm_a()
457 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM… in dcn31_update_soc_for_wm_a()
458 …context->bw_ctx.dml.soc.sr_enter_plus_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A… in dcn31_update_soc_for_wm_a()
459 …context->bw_ctx.dml.soc.sr_exit_time_us = dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_t… in dcn31_update_soc_for_wm_a()
467 if (dc->clk_mgr->bw_params->wm_table.entries[WM_A].valid) { in dcn315_update_soc_for_wm_a()
472 …context->bw_ctx.dml.soc.dram_clock_change_latency_us = dc->clk_mgr->bw_params->wm_table.entries[WM… in dcn315_update_soc_for_wm_a()
474 dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_enter_plus_exit_time_us; in dcn315_update_soc_for_wm_a()
476 dc->clk_mgr->bw_params->wm_table.entries[WM_A].sr_exit_time_us; in dcn315_update_soc_for_wm_a()
|
| /Linux-v6.6/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| D | dcn20_fpu.c | 657 struct wm_table ddr4_wm_table_gs = {
694 struct wm_table lpddr4_wm_table_gs = {
731 struct wm_table lpddr4_wm_table_with_disabled_ppt = {
768 struct wm_table ddr4_wm_table_rn = {
805 struct wm_table ddr4_1R_wm_table_rn = {
842 struct wm_table lpddr4_wm_table_rn = {
2081 dc->clk_mgr->bw_params->wm_table.entries[i].sr_exit_time_us = in patch_bounding_box()
2088 dc->clk_mgr->bw_params->wm_table.entries[i].sr_enter_plus_exit_time_us = in patch_bounding_box()
2099 dc->clk_mgr->bw_params->wm_table.entries[i].pstate_latency_us = in patch_bounding_box()
2194 table_entry = &bw_params->wm_table.entries[WM_D]; in dcn21_calculate_wm()
[all …]
|
| /Linux-v6.6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| D | dcn32_clk_mgr.c | 787 if (clk_mgr->base.bw_params->wm_table.nv_entries[i].valid) { in dcn32_notify_wm_ranges()
789 …table->Watermarks.WatermarkRow[i].Flags = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_bre… in dcn32_notify_wm_ranges()
|
| /Linux-v6.6/drivers/gpu/drm/amd/pm/powerplay/hwmgr/ |
| D | vega12_hwmgr.c | 2553 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); in vega12_display_configuration_changed_task() local
2558 (uint8_t *)wm_table, TABLE_WATERMARKS, false); in vega12_display_configuration_changed_task()
|
| D | vega20_hwmgr.c | 3645 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); in vega20_display_configuration_changed_task() local
3650 (uint8_t *)wm_table, TABLE_WATERMARKS, false); in vega20_display_configuration_changed_task()
|
| D | vega10_hwmgr.c | 4926 Watermarks_t *wm_table = &(data->smc_state_table.water_marks_table); in vega10_display_configuration_changed_task() local
4931 result = smum_smc_table_manager(hwmgr, (uint8_t *)wm_table, WMTABLE, false); in vega10_display_configuration_changed_task()
|
