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Searched refs:vsync_source (Results 1 – 5 of 5) sorted by relevance

/Linux-v6.6/drivers/gpu/drm/msm/disp/dpu1/
Ddpu_hw_top.c140 if (cfg->vsync_source >= DPU_VSYNC_SOURCE_WD_TIMER_4 && in dpu_hw_setup_vsync_source()
141 cfg->vsync_source <= DPU_VSYNC_SOURCE_WD_TIMER_0) { in dpu_hw_setup_vsync_source()
142 switch (cfg->vsync_source) { in dpu_hw_setup_vsync_source()
205 reg |= (cfg->vsync_source & 0xf) << pp_offset[pp_idx]; in dpu_hw_setup_vsync_source_and_vsync_sel()
Ddpu_hw_top.h67 u32 vsync_source; member
Ddpu_hw_intf.h108 void (*vsync_sel)(struct dpu_hw_intf *intf, u32 vsync_source);
Ddpu_hw_intf.c460 u32 vsync_source) in dpu_hw_intf_vsync_sel() argument
469 DPU_REG_WRITE(c, INTF_TEAR_MDP_VSYNC_SEL, (vsync_source & 0xf)); in dpu_hw_intf_vsync_sel()
Ddpu_encoder.c716 vsync_cfg.vsync_source = DPU_VSYNC_SOURCE_WD_TIMER_0; in _dpu_encoder_update_vsync_source()
718 vsync_cfg.vsync_source = DPU_VSYNC0_SOURCE_GPIO; in _dpu_encoder_update_vsync_source()
727 vsync_cfg.vsync_source); in _dpu_encoder_update_vsync_source()