| /Linux-v6.6/arch/arm64/include/asm/ |
| D | mmu_context.h | 44 unsigned long ttbr = phys_to_ttbr(__pa_symbol(reserved_pg_dir)); in cpu_set_reserved_ttbr0_nosync() local
46 write_sysreg(ttbr, ttbr0_el1); in cpu_set_reserved_ttbr0_nosync()
216 u64 ttbr; in update_saved_ttbr0() local
222 ttbr = phys_to_ttbr(__pa_symbol(reserved_pg_dir)); in update_saved_ttbr0()
224 ttbr = phys_to_ttbr(virt_to_phys(mm->pgd)) | ASID(mm) << 48; in update_saved_ttbr0()
226 WRITE_ONCE(task_thread_info(tsk)->ttbr0, ttbr); in update_saved_ttbr0()
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| D | uaccess.h | 61 unsigned long flags, ttbr; in __uaccess_ttbr0_disable() local
64 ttbr = read_sysreg(ttbr1_el1); in __uaccess_ttbr0_disable()
65 ttbr &= ~TTBR_ASID_MASK; in __uaccess_ttbr0_disable()
67 write_sysreg(ttbr - RESERVED_SWAPPER_OFFSET, ttbr0_el1); in __uaccess_ttbr0_disable()
69 write_sysreg(ttbr, ttbr1_el1); in __uaccess_ttbr0_disable()
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| D | assembler.h | 598 .macro offset_ttbr1, ttbr, tmp
603 orr \ttbr, \ttbr, #TTBR1_BADDR_4852_OFFSET
615 .macro phys_to_ttbr, ttbr, phys
617 orr \ttbr, \phys, \phys, lsr #46
618 and \ttbr, \ttbr, #TTBR_BADDR_MASK_52
620 mov \ttbr, \phys
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| /Linux-v6.6/drivers/gpu/drm/msm/ |
| D | msm_iommu.c | 25 phys_addr_t ttbr; member
171 phys_addr_t *ttbr, int *asid) in msm_iommu_pagetable_params() argument
180 if (ttbr) in msm_iommu_pagetable_params()
181 *ttbr = pagetable->ttbr; in msm_iommu_pagetable_params()
283 pagetable->ttbr = ttbr0_cfg.arm_lpae_s1_cfg.ttbr; in msm_iommu_pagetable_create()
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| D | msm_mmu.h | 60 int msm_iommu_pagetable_params(struct msm_mmu *mmu, phys_addr_t *ttbr,
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| /Linux-v6.6/arch/arm/include/asm/ |
| D | proc-fns.h | 158 u64 ttbr; \
160 : "=r" (ttbr)); \
161 ttbr; \
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| /Linux-v6.6/include/linux/ |
| D | io-pgtable.h | 106 u64 ttbr; member
132 u32 ttbr; member
144 u64 ttbr[4]; member
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| /Linux-v6.6/drivers/iommu/arm/arm-smmu/ |
| D | arm-smmu-qcom.c | 156 cb->ttbr[0] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid); in qcom_adreno_smmu_set_ttbr0_cfg()
168 cb->ttbr[0] = pgtbl_cfg->arm_lpae_s1_cfg.ttbr; in qcom_adreno_smmu_set_ttbr0_cfg()
169 cb->ttbr[0] |= FIELD_PREP(ARM_SMMU_TTBRn_ASID, cb->cfg->asid); in qcom_adreno_smmu_set_ttbr0_cfg()
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| D | arm-smmu.c | 482 cb->ttbr[0] = pgtbl_cfg->arm_v7s_cfg.ttbr; in arm_smmu_init_context_bank()
483 cb->ttbr[1] = 0; in arm_smmu_init_context_bank()
485 cb->ttbr[0] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, in arm_smmu_init_context_bank()
487 cb->ttbr[1] = FIELD_PREP(ARM_SMMU_TTBRn_ASID, in arm_smmu_init_context_bank()
491 cb->ttbr[1] |= pgtbl_cfg->arm_lpae_s1_cfg.ttbr; in arm_smmu_init_context_bank()
493 cb->ttbr[0] |= pgtbl_cfg->arm_lpae_s1_cfg.ttbr; in arm_smmu_init_context_bank()
496 cb->ttbr[0] = pgtbl_cfg->arm_lpae_s2_cfg.vttbr; in arm_smmu_init_context_bank()
571 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_TTBR0, cb->ttbr[0]); in arm_smmu_write_context_bank()
572 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_TTBR1, cb->ttbr[1]); in arm_smmu_write_context_bank()
574 arm_smmu_cb_writeq(smmu, idx, ARM_SMMU_CB_TTBR0, cb->ttbr[0]); in arm_smmu_write_context_bank()
[all …]
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| D | arm-smmu.h | 354 u64 ttbr[2]; member
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| D | qcom_iommu.c | 291 pgtbl_cfg.arm_lpae_s1_cfg.ttbr | in qcom_iommu_init_domain()
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| /Linux-v6.6/drivers/iommu/ |
| D | ipmmu-vmsa.c | 355 u64 ttbr; in ipmmu_domain_setup_context() local
359 ttbr = domain->cfg.arm_lpae_s1_cfg.ttbr; in ipmmu_domain_setup_context()
360 ipmmu_ctx_write_root(domain, IMTTLBR0, ttbr); in ipmmu_domain_setup_context()
361 ipmmu_ctx_write_root(domain, IMTTUBR0, ttbr >> 32); in ipmmu_domain_setup_context()
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| D | apple-dart.c | 146 #define DART_TTBR(dart, sid, idx) ((dart)->hw->ttbr + \
180 u64 ttbr; member
563 pgtbl_cfg->apple_dart_cfg.ttbr[i]); in apple_dart_setup_translation()
1184 .ttbr = DART_T8020_TTBR,
1209 .ttbr = DART_T8020_TTBR,
1234 .ttbr = DART_T8110_TTBR,
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| D | io-pgtable-dart.c | 426 cfg->apple_dart_cfg.ttbr[i] = virt_to_phys(data->pgd[i]); in apple_dart_alloc_pgtable()
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| D | io-pgtable-arm-v7s.c | 873 cfg->arm_v7s_cfg.ttbr = paddr | upper_32_bits(paddr); in arm_v7s_alloc_pgtable()
875 cfg->arm_v7s_cfg.ttbr = paddr | ARM_V7S_TTBR_S | in arm_v7s_alloc_pgtable()
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| D | mtk_iommu.c | 758 writel(dom->cfg.arm_v7s_cfg.ttbr, bank->base + REG_MMU_PT_BASE_ADDR); in mtk_iommu_attach_device()
1479 writel(m4u_dom->cfg.arm_v7s_cfg.ttbr, base + REG_MMU_PT_BASE_ADDR); in mtk_iommu_runtime_resume()
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| D | msm_iommu.c | 274 SET_TTBR0(base, ctx, priv->cfg.arm_v7s_cfg.ttbr); in __program_context()
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| D | io-pgtable-arm.c | 893 cfg->arm_lpae_s1_cfg.ttbr = virt_to_phys(data->pgd); in arm_64_lpae_alloc_pgtable_s1()
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| /Linux-v6.6/drivers/gpu/drm/msm/adreno/ |
| D | a6xx_gpu.c | 106 phys_addr_t ttbr; in a6xx_set_pagetable() local
113 if (msm_iommu_pagetable_params(ctx->aspace->mmu, &ttbr, &asid)) in a6xx_set_pagetable()
127 OUT_RING(ring, CP_SMMU_TABLE_UPDATE_0_TTBR0_LO(lower_32_bits(ttbr))); in a6xx_set_pagetable()
130 CP_SMMU_TABLE_UPDATE_1_TTBR0_HI(upper_32_bits(ttbr)) | in a6xx_set_pagetable()
141 OUT_RING(ring, lower_32_bits(ttbr)); in a6xx_set_pagetable()
142 OUT_RING(ring, (asid << 16) | upper_32_bits(ttbr)); in a6xx_set_pagetable()
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| /Linux-v6.6/drivers/iommu/arm/arm-smmu-v3/ |
| D | arm-smmu-v3-sva.c | 156 cd->ttbr = virt_to_phys(mm->pgd); in arm_smmu_alloc_shared_cd()
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| D | arm-smmu-v3.h | 580 u64 ttbr; member
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| D | arm-smmu-v3.c | 1096 cdptr[1] = cpu_to_le64(cd->ttbr & CTXDESC_CD_1_TTB0_MASK); in arm_smmu_write_ctx_desc()
2117 cfg->cd.ttbr = pgtbl_cfg->arm_lpae_s1_cfg.ttbr; in arm_smmu_domain_finalise_s1()
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