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Searched refs:smu_wm_set (Results 1 – 10 of 10) sorted by relevance

/Linux-v6.6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/
Ddcn316_clk_mgr.c397 struct dcn316_watermarks *table = clk_mgr_dcn316->smu_wm_set.wm_set; in dcn316_notify_wm_ranges()
402 if (!table || clk_mgr_dcn316->smu_wm_set.mc_address.quad_part == 0) in dcn316_notify_wm_ranges()
410 clk_mgr_dcn316->smu_wm_set.mc_address.high_part); in dcn316_notify_wm_ranges()
412 clk_mgr_dcn316->smu_wm_set.mc_address.low_part); in dcn316_notify_wm_ranges()
589 clk_mgr->smu_wm_set.wm_set = (struct dcn316_watermarks *)dm_helpers_allocate_gpu_mem( in dcn316_clk_mgr_construct()
593 &clk_mgr->smu_wm_set.mc_address.quad_part); in dcn316_clk_mgr_construct()
595 if (!clk_mgr->smu_wm_set.wm_set) { in dcn316_clk_mgr_construct()
596 clk_mgr->smu_wm_set.wm_set = &dummy_wms; in dcn316_clk_mgr_construct()
597 clk_mgr->smu_wm_set.mc_address.quad_part = 0; in dcn316_clk_mgr_construct()
599 ASSERT(clk_mgr->smu_wm_set.wm_set); in dcn316_clk_mgr_construct()
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Ddcn316_clk_mgr.h39 struct dcn316_smu_watermark_set smu_wm_set; member
/Linux-v6.6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/
Dvg_clk_mgr.c446 struct watermarks *table = clk_mgr_vgh->smu_wm_set.wm_set; in vg_notify_wm_ranges()
451 if (!table || clk_mgr_vgh->smu_wm_set.mc_address.quad_part == 0) in vg_notify_wm_ranges()
459 clk_mgr_vgh->smu_wm_set.mc_address.high_part); in vg_notify_wm_ranges()
461 clk_mgr_vgh->smu_wm_set.mc_address.low_part); in vg_notify_wm_ranges()
680 clk_mgr->smu_wm_set.wm_set = (struct watermarks *)dm_helpers_allocate_gpu_mem( in vg_clk_mgr_construct()
684 &clk_mgr->smu_wm_set.mc_address.quad_part); in vg_clk_mgr_construct()
686 if (!clk_mgr->smu_wm_set.wm_set) { in vg_clk_mgr_construct()
687 clk_mgr->smu_wm_set.wm_set = &dummy_wms; in vg_clk_mgr_construct()
688 clk_mgr->smu_wm_set.mc_address.quad_part = 0; in vg_clk_mgr_construct()
690 ASSERT(clk_mgr->smu_wm_set.wm_set); in vg_clk_mgr_construct()
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Dvg_clk_mgr.h42 struct smu_watermark_set smu_wm_set; member
/Linux-v6.6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/
Ddcn31_clk_mgr.c480 struct dcn31_watermarks *table = clk_mgr_dcn31->smu_wm_set.wm_set; in dcn31_notify_wm_ranges()
485 if (!table || clk_mgr_dcn31->smu_wm_set.mc_address.quad_part == 0) in dcn31_notify_wm_ranges()
493 clk_mgr_dcn31->smu_wm_set.mc_address.high_part); in dcn31_notify_wm_ranges()
495 clk_mgr_dcn31->smu_wm_set.mc_address.low_part); in dcn31_notify_wm_ranges()
693 clk_mgr->smu_wm_set.wm_set = (struct dcn31_watermarks *)dm_helpers_allocate_gpu_mem( in dcn31_clk_mgr_construct()
697 &clk_mgr->smu_wm_set.mc_address.quad_part); in dcn31_clk_mgr_construct()
699 if (!clk_mgr->smu_wm_set.wm_set) { in dcn31_clk_mgr_construct()
700 clk_mgr->smu_wm_set.wm_set = &dummy_wms; in dcn31_clk_mgr_construct()
701 clk_mgr->smu_wm_set.mc_address.quad_part = 0; in dcn31_clk_mgr_construct()
703 ASSERT(clk_mgr->smu_wm_set.wm_set); in dcn31_clk_mgr_construct()
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Ddcn31_clk_mgr.h39 struct dcn31_smu_watermark_set smu_wm_set; member
/Linux-v6.6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/
Ddcn315_clk_mgr.c432 struct dcn315_watermarks *table = clk_mgr_dcn315->smu_wm_set.wm_set; in dcn315_notify_wm_ranges()
437 if (!table || clk_mgr_dcn315->smu_wm_set.mc_address.quad_part == 0) in dcn315_notify_wm_ranges()
445 clk_mgr_dcn315->smu_wm_set.mc_address.high_part); in dcn315_notify_wm_ranges()
447 clk_mgr_dcn315->smu_wm_set.mc_address.low_part); in dcn315_notify_wm_ranges()
616 clk_mgr->smu_wm_set.wm_set = (struct dcn315_watermarks *)dm_helpers_allocate_gpu_mem( in dcn315_clk_mgr_construct()
620 &clk_mgr->smu_wm_set.mc_address.quad_part); in dcn315_clk_mgr_construct()
622 if (!clk_mgr->smu_wm_set.wm_set) { in dcn315_clk_mgr_construct()
623 clk_mgr->smu_wm_set.wm_set = &dummy_wms; in dcn315_clk_mgr_construct()
624 clk_mgr->smu_wm_set.mc_address.quad_part = 0; in dcn315_clk_mgr_construct()
626 ASSERT(clk_mgr->smu_wm_set.wm_set); in dcn315_clk_mgr_construct()
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Ddcn315_clk_mgr.h39 struct dcn315_smu_watermark_set smu_wm_set; member
/Linux-v6.6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/
Ddcn314_clk_mgr.c498 struct dcn314_watermarks *table = clk_mgr_dcn314->smu_wm_set.wm_set; in dcn314_notify_wm_ranges()
503 if (!table || clk_mgr_dcn314->smu_wm_set.mc_address.quad_part == 0) in dcn314_notify_wm_ranges()
511 clk_mgr_dcn314->smu_wm_set.mc_address.high_part); in dcn314_notify_wm_ranges()
513 clk_mgr_dcn314->smu_wm_set.mc_address.low_part); in dcn314_notify_wm_ranges()
740 clk_mgr->smu_wm_set.wm_set = (struct dcn314_watermarks *)dm_helpers_allocate_gpu_mem( in dcn314_clk_mgr_construct()
744 &clk_mgr->smu_wm_set.mc_address.quad_part); in dcn314_clk_mgr_construct()
746 if (!clk_mgr->smu_wm_set.wm_set) { in dcn314_clk_mgr_construct()
747 clk_mgr->smu_wm_set.wm_set = &dummy_wms; in dcn314_clk_mgr_construct()
748 clk_mgr->smu_wm_set.mc_address.quad_part = 0; in dcn314_clk_mgr_construct()
750 ASSERT(clk_mgr->smu_wm_set.wm_set); in dcn314_clk_mgr_construct()
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Ddcn314_clk_mgr.h40 struct dcn314_smu_watermark_set smu_wm_set; member