| /Linux-v6.6/sound/soc/ux500/ |
| D | ux500_msp_i2s.c | 138 writel(temp_reg, msp->registers + MSP_TCF); in set_prot_desc_tx()
166 writel(temp_reg, msp->registers + MSP_RCF); in set_prot_desc_rx()
203 temp_reg = readl(msp->registers + MSP_GCR) & ~TX_CLK_POL_RISING; in configure_protocol()
205 writel(temp_reg, msp->registers + MSP_GCR); in configure_protocol()
206 temp_reg = readl(msp->registers + MSP_GCR) & ~RX_CLK_POL_RISING; in configure_protocol()
208 writel(temp_reg, msp->registers + MSP_GCR); in configure_protocol()
222 reg_val_GCR = readl(msp->registers + MSP_GCR); in setup_bitclk()
223 writel(reg_val_GCR & ~SRG_ENABLE, msp->registers + MSP_GCR); in setup_bitclk()
255 writel(temp_reg, msp->registers + MSP_SRG); in setup_bitclk()
261 reg_val_GCR = readl(msp->registers + MSP_GCR); in setup_bitclk()
[all …]
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| /Linux-v6.6/drivers/media/radio/si470x/ |
| D | radio-si470x-common.c | 185 radio->registers[SYSCONFIG2] &= ~SYSCONFIG2_BAND; in si470x_set_band()
186 radio->registers[SYSCONFIG2] |= radio->band << 6; in si470x_set_band()
203 if ((radio->registers[POWERCFG] & (POWERCFG_ENABLE|POWERCFG_DMUTE)) in si470x_set_chan()
209 radio->registers[CHANNEL] &= ~CHANNEL_CHAN; in si470x_set_chan()
210 radio->registers[CHANNEL] |= CHANNEL_TUNE | chan; in si470x_set_chan()
222 if ((radio->registers[STATUSRSSI] & STATUSRSSI_STC) == 0) in si470x_set_chan()
229 radio->registers[CHANNEL] &= ~CHANNEL_TUNE; in si470x_set_chan()
242 switch ((radio->registers[SYSCONFIG2] & SYSCONFIG2_SPACE) >> 4) { in si470x_get_step()
265 chan = radio->registers[READCHAN] & READCHAN_READCHAN; in si470x_get_freq()
327 radio->registers[POWERCFG] |= POWERCFG_SEEK; in si470x_set_seek()
[all …]
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| D | radio-si470x-i2c.c | 99 radio->registers[regnr] = __be16_to_cpu(buf[READ_INDEX(regnr)]); in si470x_get_register()
121 buf[i] = __cpu_to_be16(radio->registers[WRITE_INDEX(i)]); in si470x_set_register()
155 radio->registers[i] = __be16_to_cpu(buf[READ_INDEX(i)]); in si470x_get_all_registers()
184 radio->registers[SYSCONFIG1] |= SYSCONFIG1_RDSIEN; in si470x_fops_open()
185 radio->registers[SYSCONFIG1] |= SYSCONFIG1_STCIEN; in si470x_fops_open()
186 radio->registers[SYSCONFIG1] &= ~SYSCONFIG1_GPIO2; in si470x_fops_open()
187 radio->registers[SYSCONFIG1] |= 0x1 << 2; in si470x_fops_open()
253 if (radio->registers[STATUSRSSI] & STATUSRSSI_STC) in si470x_i2c_interrupt()
257 if ((radio->registers[SYSCONFIG1] & SYSCONFIG1_RDS) == 0) in si470x_i2c_interrupt()
268 if ((radio->registers[STATUSRSSI] & STATUSRSSI_RDSR) == 0) in si470x_i2c_interrupt()
[all …]
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| D | radio-si470x-usb.c | 253 radio->registers[regnr] = get_unaligned_be16(&radio->usb_buf[1]); in si470x_get_register()
267 put_unaligned_be16(radio->registers[regnr], &radio->usb_buf[1]); in si470x_set_register()
294 radio->registers[regnr] = get_unaligned_be16( in si470x_get_all_registers()
388 radio->registers[STATUSRSSI] = in si470x_int_in_callback()
391 if (radio->registers[STATUSRSSI] & STATUSRSSI_STC) in si470x_int_in_callback()
394 if ((radio->registers[SYSCONFIG1] & SYSCONFIG1_RDS)) { in si470x_int_in_callback()
397 radio->registers[STATUSRSSI + regnr] = in si470x_int_in_callback()
401 if ((radio->registers[STATUSRSSI] & STATUSRSSI_RDSR) == 0) { in si470x_int_in_callback()
405 if ((radio->registers[STATUSRSSI] & STATUSRSSI_RDSS) == 0) { in si470x_int_in_callback()
412 bler = (radio->registers[STATUSRSSI] & in si470x_int_in_callback()
[all …]
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| /Linux-v6.6/drivers/scsi/smartpqi/ |
| D | smartpqi_sis.c | 100 status = readl(&ctrl_info->registers->sis_firmware_status); in sis_wait_for_ctrl_ready_with_timeout()
106 &ctrl_info->registers->sis_mailbox[7])); in sis_wait_for_ctrl_ready_with_timeout()
141 status = readl(&ctrl_info->registers->sis_firmware_status); in sis_is_firmware_running()
151 readl(&ctrl_info->registers->sis_mailbox[7])); in sis_is_firmware_running()
158 return readl(&ctrl_info->registers->sis_firmware_status) & in sis_is_kernel_up()
164 return readl(&ctrl_info->registers->sis_product_identifier); in sis_get_product_id()
175 struct pqi_ctrl_registers __iomem *registers; in sis_send_sync_cmd() local
181 registers = ctrl_info->registers; in sis_send_sync_cmd()
184 writel(cmd, ®isters->sis_mailbox[0]); in sis_send_sync_cmd()
191 writel(params->mailbox[i], ®isters->sis_mailbox[i]); in sis_send_sync_cmd()
[all …]
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| /Linux-v6.6/Documentation/driver-api/media/drivers/ccs/ |
| D | ccs-regs.asc | 18 # general status registers
51 # frame format description registers
91 # analog gain description registers
110 # data format description registers
122 # general set-up registers
170 # integration time registers
174 # analog gain registers
179 # digital gain registers
182 # hdr control registers
203 # clock set-up registers
[all …]
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| /Linux-v6.6/drivers/char/agp/ |
| D | amd-k7-agp.c | 32 volatile u8 __iomem *registers; member
216 if (!amd_irongate_private.registers) { in amd_irongate_configure()
219 amd_irongate_private.registers = (volatile u8 __iomem *) ioremap(reg, 4096); in amd_irongate_configure()
220 if (!amd_irongate_private.registers) in amd_irongate_configure()
225 writel(agp_bridge->gatt_bus_addr, amd_irongate_private.registers+AMD_ATTBASE); in amd_irongate_configure()
226 readl(amd_irongate_private.registers+AMD_ATTBASE); /* PCI Posting. */ in amd_irongate_configure()
235 enable_reg = readw(amd_irongate_private.registers+AMD_GARTENABLE); in amd_irongate_configure()
237 writew(enable_reg, amd_irongate_private.registers+AMD_GARTENABLE); in amd_irongate_configure()
238 readw(amd_irongate_private.registers+AMD_GARTENABLE); /* PCI Posting. */ in amd_irongate_configure()
246 writel(1, amd_irongate_private.registers+AMD_TLBFLUSH); in amd_irongate_configure()
[all …]
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| D | sworks-agp.c | 39 volatile u8 __iomem *registers; member
240 writeb(1, serverworks_private.registers+SVWRKS_POSTFLUSH); in serverworks_tlbflush()
242 while (readb(serverworks_private.registers+SVWRKS_POSTFLUSH) == 1) { in serverworks_tlbflush()
251 writel(1, serverworks_private.registers+SVWRKS_DIRFLUSH); in serverworks_tlbflush()
253 while (readl(serverworks_private.registers+SVWRKS_DIRFLUSH) == 1) { in serverworks_tlbflush()
272 serverworks_private.registers = (volatile u8 __iomem *) ioremap(temp, 4096); in serverworks_configure()
273 if (!serverworks_private.registers) { in serverworks_configure()
278 writeb(0xA, serverworks_private.registers+SVWRKS_GART_CACHE); in serverworks_configure()
279 readb(serverworks_private.registers+SVWRKS_GART_CACHE); /* PCI Posting. */ in serverworks_configure()
281 writel(agp_bridge->gatt_bus_addr, serverworks_private.registers+SVWRKS_GATTBASE); in serverworks_configure()
[all …]
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| D | intel-gtt.c | 67 u8 __iomem *registers; member
187 intel_private.registers = ioremap(reg_addr, KB(64)); in i810_setup()
188 if (!intel_private.registers) in i810_setup()
192 intel_private.registers+I810_PGETBL_CTL); in i810_setup()
196 if ((readl(intel_private.registers+I810_DRAM_CTL) in i810_setup()
208 writel(0, intel_private.registers+I810_PGETBL_CTL); in i810_cleanup()
366 rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE); in intel_gtt_stolen_size()
439 pgetbl_ctl2 = readl(intel_private.registers+I965_PGETBL_CTL2); in i965_adjust_pgetbl_size()
441 writel(pgetbl_ctl2, intel_private.registers+I965_PGETBL_CTL2); in i965_adjust_pgetbl_size()
444 pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); in i965_adjust_pgetbl_size()
[all …]
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| /Linux-v6.6/Documentation/devicetree/bindings/mips/ |
| D | mscc.txt | 14 The SoC has a few registers (DEVCPU_GCB:CHIP_REGS) handling miscellaneous
20 - reg : Should contain registers location and length
31 The SoC has a few registers (ICPU_CFG:CPU_SYSTEM_CTRL) handling configuration of
32 the CPU: 8 general purpose registers, reset control, CPU en/disabling, CPU
37 - reg : Should contain registers location and length
47 The SoC has a few registers (HSIO) handling miscellaneous functionalities:
53 - reg : Should contain registers location and length
|
| /Linux-v6.6/drivers/gpio/ |
| D | gpio-74x164.c | 24 u32 registers; member
38 chip->registers); in __gen_74x164_write_config()
44 u8 bank = chip->registers - 1 - offset / 8; in gen_74x164_get_value()
59 u8 bank = chip->registers - 1 - offset / 8; in gen_74x164_set_value()
82 for_each_set_clump8(offset, bankmask, mask, chip->registers * 8) { in gen_74x164_set_multiple()
83 bank = chip->registers - 1 - offset / 8; in gen_74x164_set_multiple()
141 chip->registers = nregs; in gen_74x164_probe()
142 chip->gpio_chip.ngpio = GEN_74X164_NUMBER_GPIOS * chip->registers; in gen_74x164_probe()
|
| /Linux-v6.6/drivers/gpu/drm/msm/adreno/ |
| D | a6xx_gpu_state.c | 22 struct a6xx_gpu_state_obj *registers; member
483 int count = RANGE(dbgahb->registers, j); in a6xx_get_dbgahb_cluster()
485 dbgahb->registers[j] - (dbgahb->base >> 2); in a6xx_get_dbgahb_cluster()
548 cluster->registers == a660_fe_cluster) in a6xx_get_cluster()
552 cluster->registers == a6xx_ps_cluster) in a6xx_get_cluster()
566 int count = RANGE(cluster->registers, j); in a6xx_get_cluster()
568 in += CRASHDUMP_READ(in, cluster->registers[j], in a6xx_get_cluster()
678 u32 count = RANGE(regs->registers, i); in a6xx_get_crashdumper_hlsq_registers()
680 regs->registers[i] - (regs->val0 >> 2); in a6xx_get_crashdumper_hlsq_registers()
715 (regs->registers == a660_registers)) in a6xx_get_crashdumper_registers()
[all …]
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| /Linux-v6.6/Documentation/devicetree/bindings/powerpc/nintendo/ |
| D | wii.txt | 31 - reg : should contain the VI registers location and length
42 - reg : should contain the PI registers location and length
64 - reg : should contain the DSP registers location and length
76 - reg : should contain the SI registers location and length
87 - reg : should contain the AI registers location and length
97 - reg : should contain the EXI registers location and length
107 - reg : should contain the EHCI registers location and length
117 - reg : should contain the SDHCI registers location and length
126 - reg : should contain the IPC registers location and length
138 - reg : should contain the controller registers location and length
[all …]
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| D | gamecube.txt | 22 - reg : should contain the VI registers location and length
33 - reg : should contain the PI registers location and length
53 - reg : should contain the DSP registers location and length
74 - reg : should contain the DI registers location and length
85 - reg : should contain the AI registers location and length
97 - reg : should contain the SI registers location and length
107 - reg : should contain the EXI registers location and length
|
| /Linux-v6.6/Documentation/devicetree/bindings/arm/ |
| D | atmel-sysregs.txt | 1 Atmel system registers
5 - reg : Should contain registers location and length
9 - reg: Should contain registers location and length
15 - reg: Should contain registers location and length
21 - reg: Should contain registers location and length
35 - reg: Should contain registers location and length
46 - reg: Should contain registers location and length
66 - reg: Should contain registers location and length
85 - reg: Should contain registers location and length
|
| /Linux-v6.6/Documentation/arch/sh/ |
| D | register-banks.rst | 17 In the case of this type of banking, banked registers are mapped directly to
19 can still be used to reference the banked registers (as r0_bank ... r7_bank)
21 in mind when writing code that utilizes these banked registers, for obvious
23 be used rather effectively as scratch registers by the kernel.
25 Presently the kernel uses several of these registers.
28 registers when doing exception handling).
|
| /Linux-v6.6/drivers/media/platform/rockchip/rkisp1/ |
| D | rkisp1-debug.c | 67 static const struct rkisp1_debug_register registers[] = { in rkisp1_debug_dump_core_regs_show() local
83 return rkisp1_debug_dump_regs(rkisp1, m, 0, registers); in rkisp1_debug_dump_core_regs_show()
89 static const struct rkisp1_debug_register registers[] = { in rkisp1_debug_dump_isp_regs_show() local
99 return rkisp1_debug_dump_regs(rkisp1, m, 0, registers); in rkisp1_debug_dump_isp_regs_show()
105 static const struct rkisp1_debug_register registers[] = { in rkisp1_debug_dump_rsz_regs_show() local
120 return rkisp1_debug_dump_regs(rsz->rkisp1, m, rsz->regs_base, registers); in rkisp1_debug_dump_rsz_regs_show()
126 static const struct rkisp1_debug_register registers[] = { in rkisp1_debug_dump_mi_mp_show() local
138 return rkisp1_debug_dump_regs(rkisp1, m, 0, registers); in rkisp1_debug_dump_mi_mp_show()
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| /Linux-v6.6/Documentation/devicetree/bindings/arm/marvell/ |
| D | coherency-fabric.txt | 18 - reg: Should contain coherency fabric registers location and
22 fabric registers, second pair for the per-CPU fabric registers.
25 for the per-CPU fabric registers.
28 for the per-CPU fabric registers.
|
| /Linux-v6.6/drivers/media/platform/nxp/imx8-isi/ |
| D | imx8-isi-debug.c | 28 } registers[] = { in mxc_isi_debug_dump_regs_show() local
79 for (i = 0; i < ARRAY_SIZE(registers); ++i) in mxc_isi_debug_dump_regs_show()
81 registers[i].name, registers[i].offset, in mxc_isi_debug_dump_regs_show()
82 mxc_isi_read(pipe, registers[i].offset)); in mxc_isi_debug_dump_regs_show()
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| /Linux-v6.6/Documentation/devicetree/bindings/powerpc/4xx/ |
| D | ppc440spe-adma.txt | 16 - reg : <registers mapping>
17 - dcr-reg : <DCR registers range>
35 - reg : <registers mapping>
36 - dcr-reg : <DCR registers range>
65 - reg : <registers mapping>
83 - dcr-reg : <DCR registers range>
|
| /Linux-v6.6/Documentation/devicetree/bindings/interrupt-controller/ |
| D | marvell,armada-370-xp-mpic.txt | 12 - reg: Should contain PMIC registers location and length. First pair
13 for the main interrupt registers, second pair for the per-CPU
14 interrupt registers. For this last pair, to be compliant with SMP
15 support, the "virtual" must be use (For the record, these registers
16 automatically map to the interrupt controller registers of the
|
| /Linux-v6.6/Documentation/ABI/testing/ |
| D | debugfs-hisi-zip | 4 Description: Dump of compression cores related debug registers.
10 Description: Dump of decompression cores related debug registers.
16 Description: Compression/decompression core debug registers read clear
19 disable counters clear after reading of these registers.
42 Description: Dump of QM related debug registers.
50 show its debug registers in above regs.
56 Description: QM debug registers(regs) read clear control. 1 means enable
59 disable counters clear after reading of these registers.
103 Description: QM debug registers(regs) read hardware register value. This
104 node is used to show the change of the qm registers value. This
[all …]
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| /Linux-v6.6/Documentation/bpf/ |
| D | classic_vs_extended.rst | 12 - Number of registers increase from 2 to 10:
14 The old format had two registers A and X, and a hidden frame pointer. The
15 new layout extends this to be 10 internal registers and a read-only frame
16 pointer. Since 64-bit CPUs are passing arguments to functions via registers
19 function. Natively, x86_64 passes first 6 arguments in registers, aarch64/
20 sparcv9/mips64 have 7 - 8 registers for arguments; x86_64 has 6 callee saved
21 registers, and aarch64/sparcv9/mips64 have 11 or more callee saved registers.
23 Thus, all eBPF registers map one to one to HW registers on x86_64, aarch64,
30 R0 - R5 are scratch registers and eBPF program needs spill/fill them if
38 via 32-bit subregisters. All eBPF registers are 64-bit with 32-bit lower
[all …]
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| /Linux-v6.6/Documentation/devicetree/bindings/edac/ |
| D | socfpga-eccmgr.txt | 18 - reg : Address and size for ECC error interrupt clear registers.
25 - reg : Address and size for ECC error interrupt clear registers.
60 containing the ECC manager registers.
74 - reg : Address and size for ECC error interrupt clear registers.
81 - reg : Address and size for ECC block registers.
88 - reg : Address and size for ECC block registers.
96 - reg : Address and size for ECC block registers.
104 - reg : Address and size for ECC block registers.
112 - reg : Address and size for ECC block registers.
120 - reg : Address and size for ECC block registers.
[all …]
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| /Linux-v6.6/Documentation/devicetree/bindings/pci/ |
| D | mvebu-pci.txt | 15 - ranges: ranges describing the MMIO registers to control the PCIe
21 The ranges describing the MMIO registers have the following layout:
28 registers of this PCIe interface, from the base of the internal
29 registers.
32 registers area. This range entry translates the '0x82000000 0 r' PCI
62 - assigned-addresses: reference to the MMIO registers used to control
103 <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 /* Port 0.0 registers */
104 0x82000000 0 0x42000 MBUS_ID(0xf0, 0x01) 0x42000 0 0x00002000 /* Port 2.0 registers */
105 0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000 /* Port 0.1 registers */
106 0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000 /* Port 0.2 registers */
[all …]
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