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Searched refs:regUVD_VCPU_CACHE_OFFSET1 (Results 1 – 5 of 5) sorted by relevance

/Linux-v6.6/drivers/gpu/drm/amd/amdgpu/
Dvcn_v4_0_3.c368 WREG32_SOC15(VCN, vcn_inst, regUVD_VCPU_CACHE_OFFSET1, 0); in vcn_v4_0_3_mc_resume()
464 VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
471 VCN, 0, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
934 regUVD_VCPU_CACHE_OFFSET1), 0); in vcn_v4_0_3_start_sriov()
Dvcn_v4_0.c406 WREG32_SOC15(VCN, inst, regUVD_VCPU_CACHE_OFFSET1, 0); in vcn_v4_0_mc_resume()
492 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
499 VCN, inst_idx, regUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
1306 regUVD_VCPU_CACHE_OFFSET1), in vcn_v4_0_start_sriov()
/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_2_6_0_offset.h34 #define regUVD_VCPU_CACHE_OFFSET1 macro
Dvcn_4_0_0_offset.h382 #define regUVD_VCPU_CACHE_OFFSET1 macro
Dvcn_4_0_3_offset.h384 #define regUVD_VCPU_CACHE_OFFSET1 macro