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Searched refs:regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW (Results 1 – 5 of 5) sorted by relevance

/Linux-v6.6/drivers/gpu/drm/amd/amdgpu/
Dvcn_v4_0_3.c364 WREG32_SOC15(VCN, vcn_inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, in vcn_v4_0_3_mc_resume()
458 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), in vcn_v4_0_3_mc_resume_dpg_mode()
467 VCN, 0, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v4_0_3_mc_resume_dpg_mode()
930 regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), lower_32_bits(cache_addr)); in vcn_v4_0_3_start_sriov()
Dvcn_v4_0.c402 WREG32_SOC15(VCN, inst, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW, in vcn_v4_0_mc_resume()
486 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), in vcn_v4_0_mc_resume_dpg_mode()
495 VCN, inst_idx, regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect); in vcn_v4_0_mc_resume_dpg_mode()
1300 regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), in vcn_v4_0_start_sriov()
/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_2_6_0_offset.h302 #define regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW macro
Dvcn_4_0_0_offset.h668 #define regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW macro
Dvcn_4_0_3_offset.h670 #define regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW macro