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Searched refs:regRLC_SPM_MC_CNTL (Results 1 – 6 of 6) sorted by relevance

/Linux-v6.6/drivers/gpu/drm/amd/amdgpu/
Dgfx_v9_4_3.c1327 reg = SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL); in gfx_v9_4_3_update_spm_vmid()
1337 WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); in gfx_v9_4_3_update_spm_vmid()
1339 WREG32_SOC15(GC, GET_INST(GC, 0), regRLC_SPM_MC_CNTL, data); in gfx_v9_4_3_update_spm_vmid()
Dgfx_v11_0.c4960 reg = SOC15_REG_OFFSET(GC, 0, regRLC_SPM_MC_CNTL); in gfx_v11_0_update_spm_vmid()
4970 WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data); in gfx_v11_0_update_spm_vmid()
4972 WREG32_SOC15(GC, 0, regRLC_SPM_MC_CNTL, data); in gfx_v11_0_update_spm_vmid()
/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_4_2_offset.h5046 #define regRLC_SPM_MC_CNTL … macro
Dgc_9_4_3_offset.h6560 #define regRLC_SPM_MC_CNTL … macro
Dgc_11_0_0_offset.h10566 #define regRLC_SPM_MC_CNTL … macro
Dgc_11_0_3_offset.h11198 #define regRLC_SPM_MC_CNTL … macro