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Searched refs:regMP1_SMN_IH_SW_INT_CTRL (Results 1 – 8 of 8) sorted by relevance

/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/mp/
Dmp_13_0_4_offset.h380 #define regMP1_SMN_IH_SW_INT_CTRL … macro
Dmp_13_0_2_offset.h387 #define regMP1_SMN_IH_SW_INT_CTRL … macro
Dmp_13_0_8_offset.h382 #define regMP1_SMN_IH_SW_INT_CTRL … macro
Dmp_13_0_0_offset.h379 #define regMP1_SMN_IH_SW_INT_CTRL … macro
Dmp_13_0_6_offset.h380 #define regMP1_SMN_IH_SW_INT_CTRL … macro
Dmp_13_0_5_offset.h381 #define regMP1_SMN_IH_SW_INT_CTRL … macro
/Linux-v6.6/drivers/gpu/drm/amd/pm/swsmu/smu13/
Dsmu_v13_0_6_ppt.c1284 data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL); in smu_v13_0_6_irq_process()
1286 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data); in smu_v13_0_6_irq_process()
1331 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL); in smu_v13_0_6_set_irq_state()
1333 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val); in smu_v13_0_6_set_irq_state()
1343 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL); in smu_v13_0_6_set_irq_state()
1345 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val); in smu_v13_0_6_set_irq_state()
Dsmu_v13_0.c1277 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL); in smu_v13_0_set_irq_state()
1279 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val); in smu_v13_0_set_irq_state()
1310 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL); in smu_v13_0_set_irq_state()
1312 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val); in smu_v13_0_set_irq_state()
1372 data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL); in smu_v13_0_irq_process()
1374 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data); in smu_v13_0_irq_process()