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Searched refs:regCP_HQD_PQ_DOORBELL_CONTROL (Results 1 – 9 of 9) sorted by relevance

/Linux-v6.6/drivers/gpu/drm/amd/amdgpu/
Dmes_v11_0.c828 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); in mes_v11_0_queue_init_register()
831 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); in mes_v11_0_queue_init_register()
862 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, in mes_v11_0_queue_init_register()
1123 data = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); in mes_v11_0_kiq_dequeue()
1128 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, data); in mes_v11_0_kiq_dequeue()
1130 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, 0); in mes_v11_0_kiq_dequeue()
Damdgpu_amdkfd_gc_9_4_3.c309 WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), regCP_HQD_PQ_DOORBELL_CONTROL), in kgd_gfx_v9_4_3_hqd_load()
Damdgpu_amdkfd_gfx_v11.c205 WREG32(SOC15_REG_OFFSET(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL), data); in hqd_load_v11()
Dgfx_v9_4_3.c1504 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL); in gfx_v9_4_3_xcc_mqd_init()
1618 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, in gfx_v9_4_3_xcc_kiq_init_register()
1687 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, in gfx_v9_4_3_xcc_kiq_init_register()
1743 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000); in gfx_v9_4_3_xcc_q_fini_register()
1744 WREG32_SOC15_RLC(GC, GET_INST(GC, xcc_id), regCP_HQD_PQ_DOORBELL_CONTROL, 0); in gfx_v9_4_3_xcc_q_fini_register()
Dgfx_v11_0.c3758 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); in gfx_v11_0_compute_mqd_init()
3822 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL); in gfx_v11_0_compute_mqd_init()
3884 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, in gfx_v11_0_kiq_init_register()
3945 WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL, in gfx_v11_0_kiq_init_register()
/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_4_2_offset.h723 #define regCP_HQD_PQ_DOORBELL_CONTROL … macro
Dgc_9_4_3_offset.h3312 #define regCP_HQD_PQ_DOORBELL_CONTROL … macro
Dgc_11_0_0_offset.h4630 #define regCP_HQD_PQ_DOORBELL_CONTROL … macro
Dgc_11_0_3_offset.h4854 #define regCP_HQD_PQ_DOORBELL_CONTROL … macro