Searched refs:ref_clks (Results 1 – 5 of 5) sorted by relevance
61 static const struct pic32_ref_osc_data ref_clks[] = { variable217 clks[nr_clks] = pic32_refo_clk_register(&ref_clks[i], core); in pic32mzda_clk_probe()
933 refclk = dev_priv->display.dpll.ref_clks.nssc; in hsw_ddi_wrpll_get_freq()943 refclk = dev_priv->display.dpll.ref_clks.ssc; in hsw_ddi_wrpll_get_freq()1165 i915->display.dpll.ref_clks.ssc = 135000; in hsw_update_dpll_ref_clks()1168 i915->display.dpll.ref_clks.nssc = 24000; in hsw_update_dpll_ref_clks()1170 i915->display.dpll.ref_clks.nssc = 135000; in hsw_update_dpll_ref_clks()1634 int ref_clock = i915->display.dpll.ref_clks.nssc; in skl_ddi_wrpll_get_freq()1717 i915->display.dpll.ref_clks.nssc, &wrpll_params); in skl_ddi_hdmi_pll_dividers()1873 i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref; in skl_update_dpll_ref_clks()2162 chv_calc_dpll_params(i915->display.dpll.ref_clks.nssc, clk_div); in bxt_ddi_dp_pll_dividers()2250 return chv_calc_dpll_params(i915->display.dpll.ref_clks.nssc, &clock); in bxt_ddi_pll_get_freq()[all …]
130 } ref_clks; member
649 dev_priv->display.dpll.ref_clks.nssc, in i915_shared_dplls_info()650 dev_priv->display.dpll.ref_clks.ssc); in i915_shared_dplls_info()
507 refclk = vgpu->gvt->gt->i915->display.dpll.ref_clks.ssc; in bdw_vgpu_get_dp_bitrate()538 int refclk = vgpu->gvt->gt->i915->display.dpll.ref_clks.nssc; in bxt_vgpu_get_dp_bitrate()
