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/Linux-v6.6/arch/arm/boot/dts/st/
Dstm32h743.dtsi45 #include <dt-bindings/mfd/stm32h7-rcc.h>
77 clocks = <&rcc TIM5_CK>;
85 clocks = <&rcc LPTIM1_CK>;
113 resets = <&rcc STM32H7_APB1L_RESET(SPI2)>;
114 clocks = <&rcc SPI2_CK>;
125 resets = <&rcc STM32H7_APB1L_RESET(SPI3)>;
126 clocks = <&rcc SPI3_CK>;
135 clocks = <&rcc USART2_CK>;
143 clocks = <&rcc USART3_CK>;
151 clocks = <&rcc UART4_CK>;
[all …]
Dstm32f746.dtsi45 #include <dt-bindings/mfd/stm32f7-rcc.h>
83 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM2)>;
105 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM3)>;
127 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM4)>;
149 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM5)>;
171 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM6)>;
187 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM7)>;
203 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM12)>;
223 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM13)>;
237 clocks = <&rcc 0 STM32F7_APB1_CLOCK(TIM14)>;
[all …]
Dstm32f429.dtsi50 #include <dt-bindings/mfd/stm32f4-rcc.h>
101 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM2)>;
123 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM3)>;
145 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM4)>;
167 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM5)>;
189 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM6)>;
205 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM7)>;
221 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM12)>;
241 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM13)>;
255 clocks = <&rcc 0 STM32F4_APB1_CLOCK(TIM14)>;
[all …]
Dstm32mp151.dtsi132 clocks = <&rcc TIM2_K>;
167 clocks = <&rcc TIM3_K>;
203 clocks = <&rcc TIM4_K>;
237 clocks = <&rcc TIM5_K>;
273 clocks = <&rcc TIM6_K>;
293 clocks = <&rcc TIM7_K>;
313 clocks = <&rcc TIM12_K>;
337 clocks = <&rcc TIM13_K>;
361 clocks = <&rcc TIM14_K>;
384 clocks = <&rcc LPTIM1_K>;
[all …]
Dstm32mp131.dtsi117 clocks = <&rcc TIM2_K>;
152 clocks = <&rcc TIM3_K>;
188 clocks = <&rcc TIM4_K>;
222 clocks = <&rcc TIM5_K>;
258 clocks = <&rcc TIM6_K>;
278 clocks = <&rcc TIM7_K>;
297 clocks = <&rcc LPTIM1_K>;
340 clocks = <&rcc SPI2_K>;
341 resets = <&rcc SPI2_R>;
365 clocks = <&rcc SPI3_K>;
[all …]
Dstm32mp157.dtsi15 clocks = <&rcc GPU>, <&rcc GPU_K>;
17 resets = <&rcc GPU_R>;
23 clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>;
26 resets = <&rcc DSI_R>;
Dstm32mp157c-ev1-scmi.dts40 clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
58 clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
62 clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
76 &rcc {
77 compatible = "st,stm32mp1-rcc-secure", "syscon";
Dstm32mp157a-dk1-scmi.dts33 clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
51 clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
65 &rcc {
66 compatible = "st,stm32mp1-rcc-secure", "syscon";
Dstm32mp157c-dk2-scmi.dts39 clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
57 clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
71 &rcc {
72 compatible = "st,stm32mp1-rcc-secure", "syscon";
Dstm32mp157c-ed1-scmi.dts38 clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
56 clocks = <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>;
70 &rcc {
71 compatible = "st,stm32mp1-rcc-secure", "syscon";
Dstm32mp153.dtsi40 clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
53 clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>;
Dstm32f7-pinctrl.dtsi8 #include <dt-bindings/mfd/stm32f7-rcc.h>
25 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOA)>;
35 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOB)>;
45 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOC)>;
55 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOD)>;
65 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOE)>;
75 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOF)>;
85 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOG)>;
95 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOH)>;
105 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(GPIOI)>;
[all …]
Dstm32mp133.dtsi18 clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
31 clocks = <&scmi_clk CK_SCMI_HSE>, <&rcc FDCAN_K>;
41 clocks = <&rcc ADC1>, <&rcc ADC1_K>;
Dstm32f4-pinctrl.dtsi44 #include <dt-bindings/mfd/stm32f4-rcc.h>
61 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>;
71 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOB)>;
81 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOC)>;
91 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOD)>;
101 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOE)>;
111 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOF)>;
121 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOG)>;
131 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOH)>;
141 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOI)>;
[all …]
Dstm32mp15xc.dtsi13 clocks = <&rcc CRYP1>;
14 resets = <&rcc CRYP1_R>;
Dstm32f469.dtsi11 resets = <&rcc STM32F4_APB2_RESET(DSI)>;
13 clocks = <&rcc 1 CLK_F469_DSI>, <&clk_hse>;
Dstm32mp13xf.dtsi13 clocks = <&rcc CRYP1>;
14 resets = <&rcc CRYP1_R>;
Dstm32mp13xc.dtsi13 clocks = <&rcc CRYP1>;
14 resets = <&rcc CRYP1_R>;
Dstm32mp157c-odyssey.dts39 assigned-clocks = <&rcc ETHCK_K>, <&rcc PLL4_P>;
40 assigned-clock-parents = <&rcc PLL4_P>;
Dstm32f769-disco.dts91 clocks = <&rcc 0 STM32F7_AHB1_CLOCK(OTGHSULPI)>;
103 &rcc {
104 compatible = "st,stm32f769-rcc", "st,stm32f746-rcc", "st,stm32-rcc";
Dstm32mp15xx-dhcor-avenger96.dtsi265 clocks = <&rcc CK_MCO1>;
267 assigned-clocks = <&rcc CK_MCO1>;
268 assigned-clock-parents = <&rcc CK_HSE>;
368 clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
378 clocks = <&rcc SAI2_K>;
Dstm32mp15xx-dhcom-pdk2.dtsi231 clocks = <&rcc SAI2>, <&rcc PLL3_Q>, <&rcc PLL3_R>;
241 clocks = <&rcc SAI2_K>;
259 clocks = <&rcc SAI2_K>, <&sai2a>;
/Linux-v6.6/drivers/clk/qcom/
Dclk-rpm.c257 struct rpm_cc *rcc = r->rpm_cc; in clk_rpm_xo_prepare() local
261 mutex_lock(&rcc->xo_lock); in clk_rpm_xo_prepare()
263 value = rcc->xo_buffer_value | (QCOM_RPM_XO_MODE_ON << r->xo_offset); in clk_rpm_xo_prepare()
267 rcc->xo_buffer_value = value; in clk_rpm_xo_prepare()
270 mutex_unlock(&rcc->xo_lock); in clk_rpm_xo_prepare()
278 struct rpm_cc *rcc = r->rpm_cc; in clk_rpm_xo_unprepare() local
282 mutex_lock(&rcc->xo_lock); in clk_rpm_xo_unprepare()
284 value = rcc->xo_buffer_value & ~(QCOM_RPM_XO_MODE_ON << r->xo_offset); in clk_rpm_xo_unprepare()
288 rcc->xo_buffer_value = value; in clk_rpm_xo_unprepare()
291 mutex_unlock(&rcc->xo_lock); in clk_rpm_xo_unprepare()
[all …]
/Linux-v6.6/Documentation/devicetree/bindings/clock/
Dst,stm32-rcc.txt11 "st,stm32f42xx-rcc"
12 "st,stm32f469-rcc"
13 "st,stm32f746-rcc"
14 "st,stm32f769-rcc"
29 rcc: rcc@40023800 {
32 compatible = "st,stm32f42xx-rcc", "st,stm32-rcc";
53 - include/dt-bindings/mfd/stm32f4-rcc.h
59 clocks = <&rcc 0 STM32F4_AHB1_CLOCK(GPIOA)>
64 clocks = <&rcc 0 STM32F4_AHB2_CLOCK(CRYP)>
117 clocks = <&rcc 1 STM32F4_APB1_CLOCK(TIM2)>
[all …]
Dst,stm32h7-rcc.txt11 "st,stm32h743-rcc"
31 rcc: reset-clock-controller@58024400 {
32 compatible = "st,stm32h743-rcc", "st,stm32-rcc";
50 clocks = <&rcc TIM5_CK>;
70 resets = <&rcc STM32H7_APB1L_RESET(TIM2)>;

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