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Searched refs:rFPGA0_TxGainStage (Results 1 – 7 of 7) sorted by relevance

/Linux-v6.6/drivers/staging/rtl8192u/
Dr819xU_phyreg.h9 #define rFPGA0_TxGainStage 0x80c macro
Dr819xU_phy.c601 priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; in rtl8192_InitBBRFRegDef()
602 priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; in rtl8192_InitBBRFRegDef()
603 priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; in rtl8192_InitBBRFRegDef()
604 priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; in rtl8192_InitBBRFRegDef()
803 rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC), in rtl8192_BB_Config_ParaFile()
/Linux-v6.6/drivers/staging/rtl8192e/rtl8192e/
Dr8192E_phyreg.h47 #define rFPGA0_TxGainStage 0x80c macro
Dr8192E_phy.c409 rtl92e_set_bb_reg(dev, rFPGA0_TxGainStage, in _rtl92e_bb_config_para_file()
/Linux-v6.6/drivers/staging/rtl8712/
Drtl871x_mp_phy_regdef.h89 #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */ macro
Drtl871x_mp.c319 set_bb_reg(pAdapter, rFPGA0_TxGainStage, in r8712_SetTxAGCOffset()
/Linux-v6.6/drivers/staging/rtl8723bs/include/
DHal8192CPhyReg.h97 #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */ macro