Searched refs:pllclk (Results 1 – 6 of 6) sorted by relevance
| /Linux-v6.6/arch/mips/pic32/pic32mzda/ |
| D | early_clk.c | 31 u32 pllclk; in pic32_get_sysclk() local
54 pllclk = plliclk ? FRC_CLK : PIC32_POSC_FREQ; in pic32_get_sysclk()
72 osc_freq = ((pllclk / pllidiv) * pllmult) / pllodiv; in pic32_get_sysclk()
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| /Linux-v6.6/drivers/clk/starfive/ |
| D | clk-starfive-jh7110-sys.c | 393 struct clk *pllclk; in jh7110_syscrg_probe() local
408 pllclk = clk_get(priv->dev, "pll0_out"); in jh7110_syscrg_probe()
409 if (IS_ERR(pllclk)) { in jh7110_syscrg_probe()
416 clk_put(pllclk); in jh7110_syscrg_probe()
420 pllclk = clk_get(priv->dev, "pll1_out"); in jh7110_syscrg_probe()
421 if (IS_ERR(pllclk)) { in jh7110_syscrg_probe()
428 clk_put(pllclk); in jh7110_syscrg_probe()
432 pllclk = clk_get(priv->dev, "pll2_out"); in jh7110_syscrg_probe()
433 if (IS_ERR(pllclk)) { in jh7110_syscrg_probe()
440 clk_put(pllclk); in jh7110_syscrg_probe()
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| /Linux-v6.6/drivers/clk/ |
| D | clk-xgene.c | 60 struct xgene_clk_pll *pllclk = to_xgene_clk_pll(hw); in xgene_clk_pll_is_enabled() local
63 data = xgene_clk_read(pllclk->reg + pllclk->pll_offset); in xgene_clk_pll_is_enabled()
73 struct xgene_clk_pll *pllclk = to_xgene_clk_pll(hw); in xgene_clk_pll_recalc_rate() local
81 pll = xgene_clk_read(pllclk->reg + pllclk->pll_offset); in xgene_clk_pll_recalc_rate()
83 if (pllclk->version <= 1) { in xgene_clk_pll_recalc_rate()
84 if (pllclk->type == PLL_TYPE_PCP) { in xgene_clk_pll_recalc_rate()
113 pllclk->version); in xgene_clk_pll_recalc_rate()
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| /Linux-v6.6/arch/riscv/boot/dts/starfive/ |
| D | jh7110.dtsi | 778 <&pllclk JH7110_PLLCLK_PLL0_OUT>,
779 <&pllclk JH7110_PLLCLK_PLL1_OUT>,
780 <&pllclk JH7110_PLLCLK_PLL2_OUT>;
795 pllclk: clock-controller { label
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| /Linux-v6.6/arch/arm64/boot/dts/renesas/ |
| D | r9a07g054.dtsi | 794 clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk";
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| D | r9a07g044.dtsi | 789 clock-names = "pllclk", "sysclk", "aclk", "pclk", "vclk", "lpclk";
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