Searched refs:pl2 (Results 1 – 3 of 3) sorted by relevance
86 pmd_t pl2, *pl2p = (pmd_t *)__pa(initial_pg_pmd); in mk_early_pgtbl_32() local87 #define SET_PL2(pl2, val) { (pl2).pmd = (val); } in mk_early_pgtbl_32() argument89 pgd_t pl2, *pl2p = (pgd_t *)__pa(initial_page_table); in mk_early_pgtbl_32() local90 #define SET_PL2(pl2, val) { (pl2).pgd = (val); } in mk_early_pgtbl_32() argument98 SET_PL2(pl2, (unsigned long)ptep | PDE_IDENT_ATTR); in mk_early_pgtbl_32()99 *pl2p = pl2; in mk_early_pgtbl_32()102 *(pl2p + ((PAGE_OFFSET >> PGDIR_SHIFT))) = pl2; in mk_early_pgtbl_32()
4684 const struct smu7_performance_level *pl2) in smu7_are_power_levels_equal() argument4686 return ((pl1->memory_clock == pl2->memory_clock) && in smu7_are_power_levels_equal()4687 (pl1->engine_clock == pl2->engine_clock) && in smu7_are_power_levels_equal()4688 (pl1->pcie_gen == pl2->pcie_gen) && in smu7_are_power_levels_equal()4689 (pl1->pcie_lane == pl2->pcie_lane)); in smu7_are_power_levels_equal()
4978 const struct vega10_performance_level *pl2) in vega10_are_power_levels_equal() argument4980 return ((pl1->soc_clock == pl2->soc_clock) && in vega10_are_power_levels_equal()4981 (pl1->gfx_clock == pl2->gfx_clock) && in vega10_are_power_levels_equal()4982 (pl1->mem_clock == pl2->mem_clock)); in vega10_are_power_levels_equal()
