Searched refs:pagetables (Results 1 – 13 of 13) sorted by relevance
32 bool "Three-level pagetables" if !64BIT35 Three-level pagetables will let UML have more than 4G of physical
15 atomic_t pagetables; member163 if (atomic_dec_return(&iommu->pagetables) == 0) in msm_iommu_pagetable_destroy()271 if (atomic_inc_return(&iommu->pagetables) == 1) { in msm_iommu_pagetable_create()399 atomic_set(&iommu->pagetables, 0); in msm_iommu_new()
157 # Setup trampoline 4 level pagetables
58 RESERVE_BRK(pagetables, INIT_MAP_SIZE)
57 Code walking pagetables but unaware about huge pmds can simply call66 If you're not walking pagetables but you run into a physical hugepage
126 # in the pagetables
37 nested pagetables but almost always also on bare metal without42 virtualization and nested pagetables the TLB can be mapped of
772 * GPU to update the SMMU pagetables for context switches. Work
1146 # "powerpc/mm: Allow more flexible layouts for hugepage pagetables"
1373 (kernel_stack, pagetables, percpu, vmalloc, slab) in1379 pagetables
3845 pagetables) support.
1310 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1643 bool "Allocate 3rd-level pagetables from highmem"
