Searched refs:num_compute_rings (Results 1 – 11 of 11) sorted by relevance
200 if (adev->gfx.num_compute_rings > 1 && in amdgpu_gfx_is_high_priority_compute_queue()213 adev->gfx.num_compute_rings); in amdgpu_gfx_compute_queue_acquire()443 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in amdgpu_gfx_mqd_sw_init()444 j = i + xcc_id * adev->gfx.num_compute_rings; in amdgpu_gfx_mqd_sw_init()484 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in amdgpu_gfx_mqd_sw_fini()485 j = i + xcc_id * adev->gfx.num_compute_rings; in amdgpu_gfx_mqd_sw_fini()512 adev->gfx.num_compute_rings)) { in amdgpu_gfx_disable_kcq()517 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in amdgpu_gfx_disable_kcq()518 j = i + xcc_id * adev->gfx.num_compute_rings; in amdgpu_gfx_disable_kcq()608 adev->gfx.num_compute_rings + in amdgpu_gfx_enable_kcq()[all …]
469 adev->gfx.num_compute_rings * num_xcc * GFX9_MEC_HPD_SIZE; in gfx_v9_4_3_mec_init()747 ring = &adev->gfx.compute_ring[xcc_id * adev->gfx.num_compute_rings + in gfx_v9_4_3_compute_ring_init()762 (ring_id + xcc_id * adev->gfx.num_compute_rings) * in gfx_v9_4_3_compute_ring_init()883 for (i = 0; i < adev->gfx.num_compute_rings * num_xcc; i++) in gfx_v9_4_3_sw_fini()1842 for (j = 0; j < adev->gfx.num_compute_rings; j++) { in gfx_v9_4_3_xcc_kcq_fini_register()1843 ring = &adev->gfx.compute_ring[j + xcc_id * adev->gfx.num_compute_rings]; in gfx_v9_4_3_xcc_kcq_fini_register()1889 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v9_4_3_xcc_kcq_resume()1890 ring = &adev->gfx.compute_ring[i + xcc_id * adev->gfx.num_compute_rings]; in gfx_v9_4_3_xcc_kcq_resume()1934 for (j = 0; j < adev->gfx.num_compute_rings; j++) { in gfx_v9_4_3_xcc_cp_resume()1936 [j + xcc_id * adev->gfx.num_compute_rings]; in gfx_v9_4_3_xcc_cp_resume()[all …]
290 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in suspend_resume_compute_scheduler()
1312 mec_hpd_size = adev->gfx.num_compute_rings * GFX8_MEC_HPD_SIZE; in gfx_v8_0_mec_init()2051 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v8_0_sw_fini()4337 r = amdgpu_ring_alloc(kiq_ring, (8 * adev->gfx.num_compute_rings) + 8); in gfx_v8_0_kiq_kcq_enable()4351 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_kiq_kcq_enable()4705 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_kcq_resume()4748 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_cp_test_all_rings()4812 r = amdgpu_ring_alloc(kiq_ring, 6 * adev->gfx.num_compute_rings); in gfx_v8_0_kcq_disable()4816 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_kcq_disable()5015 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_pre_soft_reset()5110 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v8_0_post_soft_reset()[all …]
2712 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v7_0_cp_compute_fini()3053 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v7_0_cp_compute_resume()3063 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v7_0_cp_compute_resume()4181 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), in gfx_v7_0_early_init()4487 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v7_0_sw_fini()4838 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v7_0_eop_irq()4863 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v7_0_fault()5053 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v7_0_set_ring_funcs()
395 unsigned num_compute_rings; member
728 mec_hpd_size = adev->gfx.num_compute_rings * GFX11_MEC_HPD_SIZE; in gfx_v11_0_mec_init()1500 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v11_0_sw_fini()4071 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v11_0_kcq_resume()4150 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v11_0_cp_resume()4558 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v11_0_check_soft_reset()4641 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), in gfx_v11_0_early_init()5876 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v11_0_eop_irq()5954 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v11_0_handle_priv_fault()6206 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v11_0_set_ring_funcs()
1696 mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE; in gfx_v9_0_mec_init()2192 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v9_0_sw_fini()3638 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v9_0_kcq_resume()3702 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v9_0_cp_resume()4518 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), in gfx_v9_0_early_init()5911 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v9_0_eop_irq()5941 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v9_0_fault()7048 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v9_0_set_ring_funcs()
3033 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), in gfx_v6_0_early_init()3085 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v6_0_sw_init()3118 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v6_0_sw_fini()3521 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v6_0_set_ring_funcs()
4207 mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE; in gfx_v10_0_mec_init()4672 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v10_0_sw_fini()6827 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v10_0_kcq_resume()6896 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v10_0_cp_resume()7424 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), in gfx_v10_0_early_init()8940 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v10_0_eop_irq()9018 for (i = 0; i < adev->gfx.num_compute_rings; i++) { in gfx_v10_0_handle_priv_fault()9280 for (i = 0; i < adev->gfx.num_compute_rings; i++) in gfx_v10_0_set_ring_funcs()
385 for (i = 0; i < adev->gfx.num_compute_rings; i++) in amdgpu_hw_ip_info()
