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Searched refs:mmUVD_RB_BASE_HI2 (Results 1 – 12 of 12) sorted by relevance

/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_6_0_d.h40 #define mmUVD_RB_BASE_HI2 0x3c22 macro
Duvd_7_0_offset.h86 #define mmUVD_RB_BASE_HI2 … macro
/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h208 #define mmUVD_RB_BASE_HI2 … macro
Dvcn_2_5_offset.h563 #define mmUVD_RB_BASE_HI2 … macro
Dvcn_2_0_0_offset.h920 #define mmUVD_RB_BASE_HI2 … macro
Dvcn_3_0_0_offset.h893 #define mmUVD_RB_BASE_HI2 … macro
/Linux-v6.6/drivers/gpu/drm/amd/amdgpu/
Dvcn_v1_0.c955 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vcn_v1_0_start_spg_mode()
1255 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vcn_v1_0_pause_dpg_mode()
Dvcn_v2_0.c1096 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vcn_v2_0_start()
1249 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vcn_v2_0_pause_dpg_mode()
Dvcn_v2_5.c1148 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vcn_v2_5_start()
1498 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vcn_v2_5_pause_dpg_mode()
Dvcn_v3_0.c1273 WREG32_SOC15(VCN, i, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vcn_v3_0_start()
1648 WREG32_SOC15(VCN, inst_idx, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vcn_v3_0_pause_dpg_mode()
Duvd_v6_0.c873 WREG32(mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in uvd_v6_0_start()
Duvd_v7_0.c1124 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in uvd_v7_0_start()