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Searched refs:mmUVD_MPC_SET_MUX (Results 1 – 19 of 19) sorted by relevance

/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/uvd/
Duvd_4_0_d.h55 #define mmUVD_MPC_SET_MUX 0x3D7D macro
Duvd_4_2_d.h58 #define mmUVD_MPC_SET_MUX 0x3d7d macro
Duvd_3_1_d.h60 #define mmUVD_MPC_SET_MUX 0x3d7d macro
Duvd_5_0_d.h64 #define mmUVD_MPC_SET_MUX 0x3d7d macro
Duvd_6_0_d.h80 #define mmUVD_MPC_SET_MUX 0x3d7d macro
Duvd_7_0_offset.h174 #define mmUVD_MPC_SET_MUX macro
/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/vcn/
Dvcn_1_0_offset.h354 #define mmUVD_MPC_SET_MUX macro
Dvcn_2_5_offset.h769 #define mmUVD_MPC_SET_MUX macro
Dvcn_2_0_0_offset.h604 #define mmUVD_MPC_SET_MUX macro
Dvcn_3_0_0_offset.h1149 #define mmUVD_MPC_SET_MUX macro
/Linux-v6.6/drivers/gpu/drm/amd/amdgpu/
Duvd_v3_1.c366 WREG32(mmUVD_MPC_SET_MUX, 0x88); in uvd_v3_1_start()
Duvd_v4_2.c322 WREG32(mmUVD_MPC_SET_MUX, 0x88); in uvd_v4_2_start()
Duvd_v5_0.c368 WREG32(mmUVD_MPC_SET_MUX, 0x88); in uvd_v5_0_start()
Dvcn_v1_0.c842 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX, in vcn_v1_0_start_spg_mode()
1025 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUX, in vcn_v1_0_start_dpg_mode()
Dvcn_v2_0.c857 UVD, 0, mmUVD_MPC_SET_MUX), in vcn_v2_0_start_dpg_mode()
990 WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX, in vcn_v2_0_start()
Dvcn_v2_5.c882 VCN, 0, mmUVD_MPC_SET_MUX), in vcn_v2_5_start_dpg_mode()
1036 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX, in vcn_v2_5_start()
Dvcn_v3_0.c1005 VCN, inst_idx, mmUVD_MPC_SET_MUX), in vcn_v3_0_start_dpg_mode()
1169 WREG32_SOC15(VCN, i, mmUVD_MPC_SET_MUX, in vcn_v3_0_start()
Duvd_v6_0.c782 WREG32(mmUVD_MPC_SET_MUX, 0x88); in uvd_v6_0_start()
Duvd_v7_0.c1024 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUX, 0x88); in uvd_v7_0_start()