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Searched refs:mmTCP_WATCH0_CNTL (Results 1 – 11 of 11) sorted by relevance

/Linux-v6.6/drivers/gpu/drm/amd/amdgpu/
Damdgpu_amdkfd_gfx_v10.c920 WREG32((SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_CNTL) + in kgd_gfx_v10_set_address_watch()
938 WREG32((SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_CNTL) + in kgd_gfx_v10_set_address_watch()
952 WREG32((SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_CNTL) + in kgd_gfx_v10_clear_address_watch()
Damdgpu_amdkfd_gfx_v9.c856 WREG32_RLC((SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_CNTL) + in kgd_gfx_v9_set_address_watch()
874 WREG32_RLC((SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_CNTL) + in kgd_gfx_v9_set_address_watch()
888 WREG32_RLC((SOC15_REG_OFFSET(GC, 0, mmTCP_WATCH0_CNTL) + in kgd_gfx_v9_clear_address_watch()
/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_7_0_d.h2142 #define mmTCP_WATCH0_CNTL 0x32a2 macro
Dgfx_7_2_d.h2163 #define mmTCP_WATCH0_CNTL 0x32a2 macro
Dgfx_8_0_d.h2355 #define mmTCP_WATCH0_CNTL 0x32a2 macro
Dgfx_8_1_d.h2334 #define mmTCP_WATCH0_CNTL 0x32a2 macro
/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h3001 #define mmTCP_WATCH0_CNTL macro
Dgc_9_1_offset.h3231 #define mmTCP_WATCH0_CNTL macro
Dgc_9_2_1_offset.h3183 #define mmTCP_WATCH0_CNTL macro
Dgc_10_1_0_offset.h5503 #define mmTCP_WATCH0_CNTL macro
Dgc_10_3_0_offset.h5138 #define mmTCP_WATCH0_CNTL macro