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Searched refs:mmSPI_WAVE_LIMIT_CNTL_BASE_IDX (Results 1 – 3 of 3) sorted by relevance

/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_2_1_offset.h5332 #define mmSPI_WAVE_LIMIT_CNTL_BASE_IDX … macro
Dgc_10_1_0_offset.h2598 #define mmSPI_WAVE_LIMIT_CNTL_BASE_IDX … macro
Dgc_10_3_0_offset.h2687 #define mmSPI_WAVE_LIMIT_CNTL_BASE_IDX … macro