Home
last modified time | relevance | path

Searched refs:mmSDMA0_RLC0_RB_RPTR (Results 1 – 16 of 16) sorted by relevance

/Linux-v6.6/drivers/gpu/drm/amd/amdgpu/
Damdgpu_amdkfd_arcturus.c159 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR, in kgd_arcturus_hqd_sdma_load()
275 m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR); in kgd_arcturus_hqd_sdma_destroy()
Damdgpu_amdkfd_gfx_v7.c268 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR, in kgd_hqd_sdma_load()
491 m->sdma_rlc_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR); in kgd_hqd_sdma_destroy()
Damdgpu_amdkfd_gfx_v8.c291 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR, in kgd_hqd_sdma_load()
526 m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR); in kgd_hqd_sdma_destroy()
Damdgpu_amdkfd_gfx_v10_3.c394 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR, in hqd_sdma_load_v10_3()
582 m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR); in hqd_sdma_destroy_v10_3()
Damdgpu_amdkfd_gfx_v10.c408 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR, in kgd_hqd_sdma_load()
658 m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR); in kgd_hqd_sdma_destroy()
Damdgpu_amdkfd_gfx_v9.c421 WREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR, in kgd_hqd_sdma_load()
610 m->sdmax_rlcx_rb_rptr = RREG32(sdma_rlc_reg_offset + mmSDMA0_RLC0_RB_RPTR); in kgd_hqd_sdma_destroy()
/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/sdma0/
Dsdma0_4_1_offset.h296 #define mmSDMA0_RLC0_RB_RPTR … macro
Dsdma0_4_0_offset.h384 #define mmSDMA0_RLC0_RB_RPTR 0x0143 macro
Dsdma0_4_2_2_offset.h384 #define mmSDMA0_RLC0_RB_RPTR … macro
Dsdma0_4_2_offset.h380 #define mmSDMA0_RLC0_RB_RPTR … macro
/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/oss/
Doss_2_4_d.h217 #define mmSDMA0_RLC0_RB_RPTR 0x3503 macro
Doss_3_0_1_d.h256 #define mmSDMA0_RLC0_RB_RPTR 0x3503 macro
Doss_3_0_d.h378 #define mmSDMA0_RLC0_RB_RPTR 0x3503 macro
Doss_2_0_d.h271 #define mmSDMA0_RLC0_RB_RPTR 0x3503 macro
/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_10_1_0_offset.h376 #define mmSDMA0_RLC0_RB_RPTR … macro
Dgc_10_3_0_offset.h374 #define mmSDMA0_RLC0_RB_RPTR … macro