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Searched refs:mmSCRATCH_REG0 (Results 1 – 16 of 16) sorted by relevance

/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_4_1_offset.h213 #define mmSCRATCH_REG0 … macro
Dgc_9_0_offset.h4641 #define mmSCRATCH_REG0 … macro
Dgc_9_1_offset.h4871 #define mmSCRATCH_REG0 … macro
Dgc_9_2_1_offset.h4827 #define mmSCRATCH_REG0 … macro
Dgc_10_1_0_offset.h7123 #define mmSCRATCH_REG0 … macro
Dgc_10_3_0_offset.h6748 #define mmSCRATCH_REG0 … macro
/Linux-v6.6/drivers/gpu/drm/amd/amdgpu/
Dgfx_v6_0.c1774 WREG32(mmSCRATCH_REG0, 0xCAFEDEAD); in gfx_v6_0_ring_test_ring()
1781 amdgpu_ring_write(ring, mmSCRATCH_REG0 - PACKET3_SET_CONFIG_REG_START); in gfx_v6_0_ring_test_ring()
1786 tmp = RREG32(mmSCRATCH_REG0); in gfx_v6_0_ring_test_ring()
1881 WREG32(mmSCRATCH_REG0, 0xCAFEDEAD); in gfx_v6_0_ring_test_ib()
1888 ib.ptr[1] = mmSCRATCH_REG0 - PACKET3_SET_CONFIG_REG_START; in gfx_v6_0_ring_test_ib()
1903 tmp = RREG32(mmSCRATCH_REG0); in gfx_v6_0_ring_test_ib()
Dgfx_v7_0.c2034 WREG32(mmSCRATCH_REG0, 0xCAFEDEAD); in gfx_v7_0_ring_test_ring()
2040 amdgpu_ring_write(ring, mmSCRATCH_REG0 - PACKET3_SET_UCONFIG_REG_START); in gfx_v7_0_ring_test_ring()
2045 tmp = RREG32(mmSCRATCH_REG0); in gfx_v7_0_ring_test_ring()
2298 WREG32(mmSCRATCH_REG0, 0xCAFEDEAD); in gfx_v7_0_ring_test_ib()
2305 ib.ptr[1] = mmSCRATCH_REG0 - PACKET3_SET_UCONFIG_REG_START; in gfx_v7_0_ring_test_ib()
2320 tmp = RREG32(mmSCRATCH_REG0); in gfx_v7_0_ring_test_ib()
Dgfx_v8_0.c845 WREG32(mmSCRATCH_REG0, 0xCAFEDEAD); in gfx_v8_0_ring_test_ring()
851 amdgpu_ring_write(ring, mmSCRATCH_REG0 - PACKET3_SET_UCONFIG_REG_START); in gfx_v8_0_ring_test_ring()
856 tmp = RREG32(mmSCRATCH_REG0); in gfx_v8_0_ring_test_ring()
Dgfx_v9_0.c997 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); in gfx_v9_0_ring_test_ring()
1638 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); in gfx_v9_0_init_rlcg_reg_access_ctrl()
Dgfx_v10_0.c3769 uint32_t scratch = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); in gfx_v10_0_ring_test_ring()
4141 reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); in gfx_v10_0_init_rlcg_reg_access_ctrl()
/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_d.h1181 #define mmSCRATCH_REG0 0x2140 macro
Dgfx_7_0_d.h404 #define mmSCRATCH_REG0 0xc040 macro
Dgfx_7_2_d.h416 #define mmSCRATCH_REG0 0xc040 macro
Dgfx_8_0_d.h454 #define mmSCRATCH_REG0 0xc040 macro
Dgfx_8_1_d.h454 #define mmSCRATCH_REG0 0xc040 macro