Home
last modified time | relevance | path

Searched refs:mmRLC_SPM_MC_CNTL (Results 1 – 7 of 7) sorted by relevance

/Linux-v6.6/drivers/gpu/drm/amd/amdgpu/
Dgfx_v9_0.c4879 reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL); in gfx_v9_0_update_spm_vmid_internal()
4883 data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL); in gfx_v9_0_update_spm_vmid_internal()
4889 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data); in gfx_v9_0_update_spm_vmid_internal()
4891 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data); in gfx_v9_0_update_spm_vmid_internal()
Dgfx_v10_0.c7903 reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL); in gfx_v10_0_update_spm_vmid_internal()
7907 data = RREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL); in gfx_v10_0_update_spm_vmid_internal()
7913 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data); in gfx_v10_0_update_spm_vmid_internal()
7915 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data); in gfx_v10_0_update_spm_vmid_internal()
/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h6115 #define mmRLC_SPM_MC_CNTL … macro
Dgc_9_1_offset.h6337 #define mmRLC_SPM_MC_CNTL … macro
Dgc_9_2_1_offset.h6315 #define mmRLC_SPM_MC_CNTL … macro
Dgc_10_1_0_offset.h9451 #define mmRLC_SPM_MC_CNTL … macro
Dgc_10_3_0_offset.h9283 #define mmRLC_SPM_MC_CNTL … macro