1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2020 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 /************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13 #ifndef ASIC_REG_NIC0_QPC0_REGS_H_ 14 #define ASIC_REG_NIC0_QPC0_REGS_H_ 15 16 /* 17 ***************************************** 18 * NIC0_QPC0 19 * (Prototype: NIC_QPC) 20 ***************************************** 21 */ 22 23 #define mmNIC0_QPC0_REQ_QPC_CACHE_INVALIDATE 0x541F000 24 25 #define mmNIC0_QPC0_REQ_QPC_CACHE_INV_STATUS 0x541F004 26 27 #define mmNIC0_QPC0_REQ_STATIC_CONFIG 0x541F008 28 29 #define mmNIC0_QPC0_REQ_BASE_ADDRESS_63_32 0x541F00C 30 31 #define mmNIC0_QPC0_REQ_BASE_ADDRESS_31_7 0x541F010 32 33 #define mmNIC0_QPC0_REQ_CLEAN_LINK_LIST 0x541F014 34 35 #define mmNIC0_QPC0_REQ_ERR_FIFO_PUSH_63_32 0x541F018 36 37 #define mmNIC0_QPC0_REQ_ERR_FIFO_PUSH_31_0 0x541F01C 38 39 #define mmNIC0_QPC0_REQ_ERR_QP_STATE_63_32 0x541F020 40 41 #define mmNIC0_QPC0_REQ_ERR_QP_STATE_31_0 0x541F024 42 43 #define mmNIC0_QPC0_RETRY_COUNT_MAX 0x541F028 44 45 #define mmNIC0_QPC0_AXI_PROT 0x541F030 46 47 #define mmNIC0_QPC0_RES_QPC_CACHE_INVALIDATE 0x541F034 48 49 #define mmNIC0_QPC0_RES_QPC_CACHE_INV_STATUS 0x541F038 50 51 #define mmNIC0_QPC0_RES_STATIC_CONFIG 0x541F03C 52 53 #define mmNIC0_QPC0_RES_BASE_ADDRESS_63_32 0x541F040 54 55 #define mmNIC0_QPC0_RES_BASE_ADDRESS_31_7 0x541F044 56 57 #define mmNIC0_QPC0_RES_CLEAN_LINK_LIST 0x541F048 58 59 #define mmNIC0_QPC0_ERR_FIFO_WRITE_INDEX 0x541F050 60 61 #define mmNIC0_QPC0_ERR_FIFO_PRODUCER_INDEX 0x541F054 62 63 #define mmNIC0_QPC0_ERR_FIFO_CONSUMER_INDEX 0x541F058 64 65 #define mmNIC0_QPC0_ERR_FIFO_MASK 0x541F05C 66 67 #define mmNIC0_QPC0_ERR_FIFO_CREDIT 0x541F060 68 69 #define mmNIC0_QPC0_ERR_FIFO_CFG 0x541F064 70 71 #define mmNIC0_QPC0_ERR_FIFO_INTR_MASK 0x541F068 72 73 #define mmNIC0_QPC0_ERR_FIFO_BASE_ADDR_63_32 0x541F06C 74 75 #define mmNIC0_QPC0_ERR_FIFO_BASE_ADDR_31_7 0x541F070 76 77 #define mmNIC0_QPC0_GW_BUSY 0x541F080 78 79 #define mmNIC0_QPC0_GW_CTRL 0x541F084 80 81 #define mmNIC0_QPC0_GW_DATA_0 0x541F08C 82 83 #define mmNIC0_QPC0_GW_DATA_1 0x541F090 84 85 #define mmNIC0_QPC0_GW_DATA_2 0x541F094 86 87 #define mmNIC0_QPC0_GW_DATA_3 0x541F098 88 89 #define mmNIC0_QPC0_GW_DATA_4 0x541F09C 90 91 #define mmNIC0_QPC0_GW_DATA_5 0x541F0A0 92 93 #define mmNIC0_QPC0_GW_DATA_6 0x541F0A4 94 95 #define mmNIC0_QPC0_GW_DATA_7 0x541F0A8 96 97 #define mmNIC0_QPC0_GW_DATA_8 0x541F0AC 98 99 #define mmNIC0_QPC0_GW_DATA_9 0x541F0B0 100 101 #define mmNIC0_QPC0_GW_DATA_10 0x541F0B4 102 103 #define mmNIC0_QPC0_GW_DATA_11 0x541F0B8 104 105 #define mmNIC0_QPC0_GW_DATA_12 0x541F0BC 106 107 #define mmNIC0_QPC0_GW_DATA_13 0x541F0C0 108 109 #define mmNIC0_QPC0_GW_DATA_14 0x541F0C4 110 111 #define mmNIC0_QPC0_GW_DATA_15 0x541F0C8 112 113 #define mmNIC0_QPC0_GW_DATA_16 0x541F0CC 114 115 #define mmNIC0_QPC0_GW_DATA_17 0x541F0D0 116 117 #define mmNIC0_QPC0_GW_DATA_18 0x541F0D4 118 119 #define mmNIC0_QPC0_GW_DATA_19 0x541F0D8 120 121 #define mmNIC0_QPC0_GW_DATA_20 0x541F0DC 122 123 #define mmNIC0_QPC0_GW_DATA_21 0x541F0E0 124 125 #define mmNIC0_QPC0_GW_DATA_22 0x541F0E4 126 127 #define mmNIC0_QPC0_GW_DATA_23 0x541F0E8 128 129 #define mmNIC0_QPC0_GW_DATA_24 0x541F0EC 130 131 #define mmNIC0_QPC0_GW_DATA_25 0x541F0F0 132 133 #define mmNIC0_QPC0_GW_DATA_26 0x541F0F4 134 135 #define mmNIC0_QPC0_GW_DATA_27 0x541F0F8 136 137 #define mmNIC0_QPC0_GW_DATA_28 0x541F0FC 138 139 #define mmNIC0_QPC0_GW_DATA_29 0x541F100 140 141 #define mmNIC0_QPC0_GW_DATA_30 0x541F104 142 143 #define mmNIC0_QPC0_GW_DATA_31 0x541F108 144 145 #define mmNIC0_QPC0_GW_MASK_0 0x541F124 146 147 #define mmNIC0_QPC0_GW_MASK_1 0x541F128 148 149 #define mmNIC0_QPC0_GW_MASK_2 0x541F12C 150 151 #define mmNIC0_QPC0_GW_MASK_3 0x541F130 152 153 #define mmNIC0_QPC0_GW_MASK_4 0x541F134 154 155 #define mmNIC0_QPC0_GW_MASK_5 0x541F138 156 157 #define mmNIC0_QPC0_GW_MASK_6 0x541F13C 158 159 #define mmNIC0_QPC0_GW_MASK_7 0x541F140 160 161 #define mmNIC0_QPC0_GW_MASK_8 0x541F144 162 163 #define mmNIC0_QPC0_GW_MASK_9 0x541F148 164 165 #define mmNIC0_QPC0_GW_MASK_10 0x541F14C 166 167 #define mmNIC0_QPC0_GW_MASK_11 0x541F150 168 169 #define mmNIC0_QPC0_GW_MASK_12 0x541F154 170 171 #define mmNIC0_QPC0_GW_MASK_13 0x541F158 172 173 #define mmNIC0_QPC0_GW_MASK_14 0x541F15C 174 175 #define mmNIC0_QPC0_GW_MASK_15 0x541F160 176 177 #define mmNIC0_QPC0_GW_MASK_16 0x541F164 178 179 #define mmNIC0_QPC0_GW_MASK_17 0x541F168 180 181 #define mmNIC0_QPC0_GW_MASK_18 0x541F16C 182 183 #define mmNIC0_QPC0_GW_MASK_19 0x541F170 184 185 #define mmNIC0_QPC0_GW_MASK_20 0x541F174 186 187 #define mmNIC0_QPC0_GW_MASK_21 0x541F178 188 189 #define mmNIC0_QPC0_GW_MASK_22 0x541F17C 190 191 #define mmNIC0_QPC0_GW_MASK_23 0x541F180 192 193 #define mmNIC0_QPC0_GW_MASK_24 0x541F184 194 195 #define mmNIC0_QPC0_GW_MASK_25 0x541F188 196 197 #define mmNIC0_QPC0_GW_MASK_26 0x541F18C 198 199 #define mmNIC0_QPC0_GW_MASK_27 0x541F190 200 201 #define mmNIC0_QPC0_GW_MASK_28 0x541F194 202 203 #define mmNIC0_QPC0_GW_MASK_29 0x541F198 204 205 #define mmNIC0_QPC0_GW_MASK_30 0x541F19C 206 207 #define mmNIC0_QPC0_GW_MASK_31 0x541F1A0 208 209 #define mmNIC0_QPC0_CC_TIMEOUT 0x541F1B0 210 211 #define mmNIC0_QPC0_CC_WINDOW_INC_EN 0x541F1FC 212 213 #define mmNIC0_QPC0_CC_TICK_WRAP 0x541F200 214 215 #define mmNIC0_QPC0_CC_ROLLBACK 0x541F204 216 217 #define mmNIC0_QPC0_CC_MAX_WINDOW_SIZE 0x541F208 218 219 #define mmNIC0_QPC0_CC_MIN_WINDOW_SIZE 0x541F20C 220 221 #define mmNIC0_QPC0_CC_ALPHA_LINEAR_0 0x541F210 222 223 #define mmNIC0_QPC0_CC_ALPHA_LINEAR_1 0x541F214 224 225 #define mmNIC0_QPC0_CC_ALPHA_LINEAR_2 0x541F218 226 227 #define mmNIC0_QPC0_CC_ALPHA_LINEAR_3 0x541F21C 228 229 #define mmNIC0_QPC0_CC_ALPHA_LINEAR_4 0x541F220 230 231 #define mmNIC0_QPC0_CC_ALPHA_LINEAR_5 0x541F224 232 233 #define mmNIC0_QPC0_CC_ALPHA_LINEAR_6 0x541F228 234 235 #define mmNIC0_QPC0_CC_ALPHA_LINEAR_7 0x541F22C 236 237 #define mmNIC0_QPC0_CC_ALPHA_LINEAR_8 0x541F230 238 239 #define mmNIC0_QPC0_CC_ALPHA_LINEAR_9 0x541F234 240 241 #define mmNIC0_QPC0_CC_ALPHA_LINEAR_10 0x541F238 242 243 #define mmNIC0_QPC0_CC_ALPHA_LINEAR_11 0x541F23C 244 245 #define mmNIC0_QPC0_CC_ALPHA_LINEAR_12 0x541F240 246 247 #define mmNIC0_QPC0_CC_ALPHA_LINEAR_13 0x541F244 248 249 #define mmNIC0_QPC0_CC_ALPHA_LINEAR_14 0x541F248 250 251 #define mmNIC0_QPC0_CC_ALPHA_LINEAR_15 0x541F24C 252 253 #define mmNIC0_QPC0_CC_ALPHA_LOG_0 0x541F250 254 255 #define mmNIC0_QPC0_CC_ALPHA_LOG_1 0x541F254 256 257 #define mmNIC0_QPC0_CC_ALPHA_LOG_2 0x541F258 258 259 #define mmNIC0_QPC0_CC_ALPHA_LOG_3 0x541F25C 260 261 #define mmNIC0_QPC0_CC_ALPHA_LOG_4 0x541F260 262 263 #define mmNIC0_QPC0_CC_ALPHA_LOG_5 0x541F264 264 265 #define mmNIC0_QPC0_CC_ALPHA_LOG_6 0x541F268 266 267 #define mmNIC0_QPC0_CC_ALPHA_LOG_7 0x541F26C 268 269 #define mmNIC0_QPC0_CC_ALPHA_LOG_8 0x541F270 270 271 #define mmNIC0_QPC0_CC_ALPHA_LOG_9 0x541F274 272 273 #define mmNIC0_QPC0_CC_ALPHA_LOG_10 0x541F278 274 275 #define mmNIC0_QPC0_CC_ALPHA_LOG_11 0x541F27C 276 277 #define mmNIC0_QPC0_CC_ALPHA_LOG_12 0x541F280 278 279 #define mmNIC0_QPC0_CC_ALPHA_LOG_13 0x541F284 280 281 #define mmNIC0_QPC0_CC_ALPHA_LOG_14 0x541F288 282 283 #define mmNIC0_QPC0_CC_ALPHA_LOG_15 0x541F28C 284 285 #define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_0 0x541F290 286 287 #define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_1 0x541F294 288 289 #define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_2 0x541F298 290 291 #define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_3 0x541F29C 292 293 #define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_4 0x541F2A0 294 295 #define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_5 0x541F2A4 296 297 #define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_6 0x541F2A8 298 299 #define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_7 0x541F2AC 300 301 #define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_8 0x541F2B0 302 303 #define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_9 0x541F2B4 304 305 #define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_10 0x541F2B8 306 307 #define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_11 0x541F2BC 308 309 #define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_12 0x541F2C0 310 311 #define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_13 0x541F2C4 312 313 #define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_14 0x541F2C8 314 315 #define mmNIC0_QPC0_CC_ALPHA_LOG_THRESHOLD_15 0x541F2CC 316 317 #define mmNIC0_QPC0_CC_WINDOW_INC_0 0x541F2D0 318 319 #define mmNIC0_QPC0_CC_WINDOW_INC_1 0x541F2D4 320 321 #define mmNIC0_QPC0_CC_WINDOW_INC_2 0x541F2D8 322 323 #define mmNIC0_QPC0_CC_WINDOW_INC_3 0x541F2DC 324 325 #define mmNIC0_QPC0_CC_WINDOW_INC_4 0x541F2E0 326 327 #define mmNIC0_QPC0_CC_WINDOW_INC_5 0x541F2E4 328 329 #define mmNIC0_QPC0_CC_WINDOW_INC_6 0x541F2E8 330 331 #define mmNIC0_QPC0_CC_WINDOW_INC_7 0x541F2EC 332 333 #define mmNIC0_QPC0_CC_WINDOW_INC_8 0x541F2F0 334 335 #define mmNIC0_QPC0_CC_WINDOW_INC_9 0x541F2F4 336 337 #define mmNIC0_QPC0_CC_WINDOW_INC_10 0x541F2F8 338 339 #define mmNIC0_QPC0_CC_WINDOW_INC_11 0x541F2FC 340 341 #define mmNIC0_QPC0_CC_WINDOW_INC_12 0x541F300 342 343 #define mmNIC0_QPC0_CC_WINDOW_INC_13 0x541F304 344 345 #define mmNIC0_QPC0_CC_WINDOW_INC_14 0x541F308 346 347 #define mmNIC0_QPC0_CC_WINDOW_INC_15 0x541F30C 348 349 #define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_0 0x541F310 350 351 #define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_1 0x541F314 352 353 #define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_2 0x541F318 354 355 #define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_3 0x541F31C 356 357 #define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_4 0x541F320 358 359 #define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_5 0x541F324 360 361 #define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_6 0x541F328 362 363 #define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_7 0x541F32C 364 365 #define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_8 0x541F330 366 367 #define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_9 0x541F334 368 369 #define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_10 0x541F338 370 371 #define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_11 0x541F33C 372 373 #define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_12 0x541F340 374 375 #define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_13 0x541F344 376 377 #define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_14 0x541F348 378 379 #define mmNIC0_QPC0_CC_WINDOW_IN_THRESHOLD_15 0x541F34C 380 381 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_0 0x541F360 382 383 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_1 0x541F364 384 385 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_2 0x541F368 386 387 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_3 0x541F36C 388 389 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_4 0x541F370 390 391 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_5 0x541F374 392 393 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_6 0x541F378 394 395 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_7 0x541F37C 396 397 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_8 0x541F380 398 399 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_9 0x541F384 400 401 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_10 0x541F388 402 403 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_11 0x541F38C 404 405 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_12 0x541F390 406 407 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_13 0x541F394 408 409 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_14 0x541F398 410 411 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_15 0x541F39C 412 413 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_16 0x541F3A0 414 415 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_17 0x541F3A4 416 417 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_18 0x541F3A8 418 419 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_19 0x541F3AC 420 421 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_20 0x541F3B0 422 423 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_21 0x541F3B4 424 425 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_22 0x541F3B8 426 427 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_23 0x541F3BC 428 429 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_24 0x541F3C0 430 431 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_25 0x541F3C4 432 433 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_26 0x541F3C8 434 435 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_27 0x541F3CC 436 437 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_28 0x541F3D0 438 439 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_29 0x541F3D4 440 441 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_30 0x541F3D8 442 443 #define mmNIC0_QPC0_DB_FIFO_USER_OVRD_31 0x541F3DC 444 445 #define mmNIC0_QPC0_DB_FIFO_CFG_0 0x541F3E0 446 447 #define mmNIC0_QPC0_DB_FIFO_CFG_1 0x541F3E4 448 449 #define mmNIC0_QPC0_DB_FIFO_CFG_2 0x541F3E8 450 451 #define mmNIC0_QPC0_DB_FIFO_CFG_3 0x541F3EC 452 453 #define mmNIC0_QPC0_DB_FIFO_CFG_4 0x541F3F0 454 455 #define mmNIC0_QPC0_DB_FIFO_CFG_5 0x541F3F4 456 457 #define mmNIC0_QPC0_DB_FIFO_CFG_6 0x541F3F8 458 459 #define mmNIC0_QPC0_DB_FIFO_CFG_7 0x541F3FC 460 461 #define mmNIC0_QPC0_DB_FIFO_CFG_8 0x541F400 462 463 #define mmNIC0_QPC0_DB_FIFO_CFG_9 0x541F404 464 465 #define mmNIC0_QPC0_DB_FIFO_CFG_10 0x541F408 466 467 #define mmNIC0_QPC0_DB_FIFO_CFG_11 0x541F40C 468 469 #define mmNIC0_QPC0_DB_FIFO_CFG_12 0x541F410 470 471 #define mmNIC0_QPC0_DB_FIFO_CFG_13 0x541F414 472 473 #define mmNIC0_QPC0_DB_FIFO_CFG_14 0x541F418 474 475 #define mmNIC0_QPC0_DB_FIFO_CFG_15 0x541F41C 476 477 #define mmNIC0_QPC0_DB_FIFO_CFG_16 0x541F420 478 479 #define mmNIC0_QPC0_DB_FIFO_CFG_17 0x541F424 480 481 #define mmNIC0_QPC0_DB_FIFO_CFG_18 0x541F428 482 483 #define mmNIC0_QPC0_DB_FIFO_CFG_19 0x541F42C 484 485 #define mmNIC0_QPC0_DB_FIFO_CFG_20 0x541F430 486 487 #define mmNIC0_QPC0_DB_FIFO_CFG_21 0x541F434 488 489 #define mmNIC0_QPC0_DB_FIFO_CFG_22 0x541F438 490 491 #define mmNIC0_QPC0_DB_FIFO_CFG_23 0x541F43C 492 493 #define mmNIC0_QPC0_DB_FIFO_CFG_24 0x541F440 494 495 #define mmNIC0_QPC0_DB_FIFO_CFG_25 0x541F444 496 497 #define mmNIC0_QPC0_DB_FIFO_CFG_26 0x541F448 498 499 #define mmNIC0_QPC0_DB_FIFO_CFG_27 0x541F44C 500 501 #define mmNIC0_QPC0_DB_FIFO_CFG_28 0x541F450 502 503 #define mmNIC0_QPC0_DB_FIFO_CFG_29 0x541F454 504 505 #define mmNIC0_QPC0_DB_FIFO_CFG_30 0x541F458 506 507 #define mmNIC0_QPC0_DB_FIFO_CFG_31 0x541F45C 508 509 #define mmNIC0_QPC0_SECURED_DB_FIRST32 0x541F460 510 511 #define mmNIC0_QPC0_SECURED_DB_SECOND32 0x541F464 512 513 #define mmNIC0_QPC0_SECURED_DB_THIRD32 0x541F468 514 515 #define mmNIC0_QPC0_SECURED_DB_FOURTH32 0x541F46C 516 517 #define mmNIC0_QPC0_PRIVILEGE_DB_FIRST32 0x541F470 518 519 #define mmNIC0_QPC0_PRIVILEGE_DB_SECOND32 0x541F474 520 521 #define mmNIC0_QPC0_PRIVILEGE_DB_THIRD32 0x541F478 522 523 #define mmNIC0_QPC0_PRIVILEGE_DB_FOURTH32 0x541F47C 524 525 #define mmNIC0_QPC0_DBG_INDICATION 0x541F480 526 527 #define mmNIC0_QPC0_WTD_WC_FSM 0x541F484 528 529 #define mmNIC0_QPC0_WTD_SLICE_FSM 0x541F488 530 531 #define mmNIC0_QPC0_REQ_TX_EMPTY_CNT 0x541F48C 532 533 #define mmNIC0_QPC0_RES_TX_EMPTY_CNT 0x541F490 534 535 #define mmNIC0_QPC0_NUM_ROLLBACKS 0x541F494 536 537 #define mmNIC0_QPC0_LAST_QP_ROLLED_BACK 0x541F498 538 539 #define mmNIC0_QPC0_NUM_TIMEOUTS 0x541F49C 540 541 #define mmNIC0_QPC0_LAST_QP_TIMED_OUT 0x541F4A0 542 543 #define mmNIC0_QPC0_WTD_SLICE_FSM_HI 0x541F4A4 544 545 #define mmNIC0_QPC0_INTERRUPT_BASE_0 0x541F4B0 546 547 #define mmNIC0_QPC0_INTERRUPT_BASE_1 0x541F4B4 548 549 #define mmNIC0_QPC0_INTERRUPT_BASE_2 0x541F4B8 550 551 #define mmNIC0_QPC0_INTERRUPT_BASE_3 0x541F4BC 552 553 #define mmNIC0_QPC0_INTERRUPT_BASE_4 0x541F4C0 554 555 #define mmNIC0_QPC0_INTERRUPT_BASE_5 0x541F4C4 556 557 #define mmNIC0_QPC0_INTERRUPT_BASE_6 0x541F4C8 558 559 #define mmNIC0_QPC0_INTERRUPT_BASE_7 0x541F4CC 560 561 #define mmNIC0_QPC0_INTERRUPT_BASE_8 0x541F4D0 562 563 #define mmNIC0_QPC0_INTERRUPT_BASE_9 0x541F4D4 564 565 #define mmNIC0_QPC0_INTERRUPT_BASE_10 0x541F4D8 566 567 #define mmNIC0_QPC0_INTERRUPT_DATA_0 0x541F4DC 568 569 #define mmNIC0_QPC0_INTERRUPT_DATA_1 0x541F4E0 570 571 #define mmNIC0_QPC0_INTERRUPT_DATA_2 0x541F4E4 572 573 #define mmNIC0_QPC0_INTERRUPT_DATA_3 0x541F4E8 574 575 #define mmNIC0_QPC0_INTERRUPT_DATA_4 0x541F4EC 576 577 #define mmNIC0_QPC0_INTERRUPT_DATA_5 0x541F4F0 578 579 #define mmNIC0_QPC0_INTERRUPT_DATA_6 0x541F4F4 580 581 #define mmNIC0_QPC0_INTERRUPT_DATA_7 0x541F4F8 582 583 #define mmNIC0_QPC0_INTERRUPT_DATA_8 0x541F4FC 584 585 #define mmNIC0_QPC0_INTERRUPT_DATA_9 0x541F500 586 587 #define mmNIC0_QPC0_INTERRUPT_DATA_10 0x541F504 588 589 #define mmNIC0_QPC0_DBG_COUNT_SELECT_0 0x541F600 590 591 #define mmNIC0_QPC0_DBG_COUNT_SELECT_1 0x541F604 592 593 #define mmNIC0_QPC0_DBG_COUNT_SELECT_2 0x541F608 594 595 #define mmNIC0_QPC0_DBG_COUNT_SELECT_3 0x541F60C 596 597 #define mmNIC0_QPC0_DBG_COUNT_SELECT_4 0x541F610 598 599 #define mmNIC0_QPC0_DBG_COUNT_SELECT_5 0x541F614 600 601 #define mmNIC0_QPC0_DBG_COUNT_SELECT_6 0x541F618 602 603 #define mmNIC0_QPC0_DBG_COUNT_SELECT_7 0x541F61C 604 605 #define mmNIC0_QPC0_DBG_COUNT_SELECT_8 0x541F620 606 607 #define mmNIC0_QPC0_DBG_COUNT_SELECT_9 0x541F624 608 609 #define mmNIC0_QPC0_DBG_COUNT_SELECT_10 0x541F628 610 611 #define mmNIC0_QPC0_DBG_COUNT_SELECT_11 0x541F62C 612 613 #define mmNIC0_QPC0_DOORBELL_SECURITY 0x541F648 614 615 #define mmNIC0_QPC0_DBG_CFG 0x541F64C 616 617 #define mmNIC0_QPC0_RES_RING0_PI 0x541F650 618 619 #define mmNIC0_QPC0_RES_RING0_CI 0x541F654 620 621 #define mmNIC0_QPC0_RES_RING0_CFG 0x541F658 622 623 #define mmNIC0_QPC0_RES_RING1_PI 0x541F65C 624 625 #define mmNIC0_QPC0_RES_RING1_CI 0x541F660 626 627 #define mmNIC0_QPC0_RES_RING1_CFG 0x541F664 628 629 #define mmNIC0_QPC0_RES_RING2_PI 0x541F668 630 631 #define mmNIC0_QPC0_RES_RING2_CI 0x541F66C 632 633 #define mmNIC0_QPC0_RES_RING2_CFG 0x541F670 634 635 #define mmNIC0_QPC0_RES_RING3_PI 0x541F674 636 637 #define mmNIC0_QPC0_RES_RING3_CI 0x541F678 638 639 #define mmNIC0_QPC0_RES_RING3_CFG 0x541F67C 640 641 #define mmNIC0_QPC0_REQ_RING0_CI 0x541F680 642 643 #define mmNIC0_QPC0_REQ_RING1_CI 0x541F684 644 645 #define mmNIC0_QPC0_REQ_RING2_CI 0x541F688 646 647 #define mmNIC0_QPC0_REQ_RING3_CI 0x541F68C 648 649 #define mmNIC0_QPC0_INTERRUPT_CAUSE 0x541F690 650 651 #define mmNIC0_QPC0_INTERRUPT_MASK 0x541F694 652 653 #define mmNIC0_QPC0_INTERRUPT_CLR 0x541F698 654 655 #define mmNIC0_QPC0_INTERRUPT_EN 0x541F69C 656 657 #define mmNIC0_QPC0_INTERRUPT_CFG 0x541F6F0 658 659 #define mmNIC0_QPC0_INTERRUPT_RESP_ERR_CAUSE 0x541F6F4 660 661 #define mmNIC0_QPC0_INTERRUPT_RESP_ERR_MASK 0x541F6F8 662 663 #define mmNIC0_QPC0_INTERRUPR_RESP_ERR_CLR 0x541F700 664 665 #define mmNIC0_QPC0_TMR_GW_VALID 0x541F704 666 667 #define mmNIC0_QPC0_TMR_GW_DATA0 0x541F708 668 669 #define mmNIC0_QPC0_TMR_GW_DATA1 0x541F70C 670 671 #define mmNIC0_QPC0_RNR_RETRY_COUNT_EN 0x541F710 672 673 #define mmNIC0_QPC0_EVENT_QUE_BASE_ADDR_63_32 0x541F830 674 675 #define mmNIC0_QPC0_EVENT_QUE_BASE_ADDR_31_7 0x541F834 676 677 #define mmNIC0_QPC0_EVENT_QUE_LOG_SIZE 0x541F838 678 679 #define mmNIC0_QPC0_EVENT_QUE_WRITE_INDEX 0x541F83C 680 681 #define mmNIC0_QPC0_EVENT_QUE_PRODUCER_INDEX 0x541F840 682 683 #define mmNIC0_QPC0_EVENT_QUE_PI_ADDR_63_32 0x541F844 684 685 #define mmNIC0_QPC0_EVENT_QUE_PI_ADDR_31_7 0x541F848 686 687 #define mmNIC0_QPC0_EVENT_QUE_CONSUMER_INDEX_CB 0x541F84C 688 689 #define mmNIC0_QPC0_EVENT_QUE_CFG 0x541F850 690 691 #define mmNIC0_QPC0_LBW_PROT 0x541F858 692 693 #define mmNIC0_QPC0_MEM_WRITE_INIT 0x541F85C 694 695 #define mmNIC0_QPC0_QMAN_DOORBELL 0x541F8E8 696 697 #define mmNIC0_QPC0_QMAN_DOORBELL_QPN 0x541F8EC 698 699 #define mmNIC0_QPC0_SECURED_CQ_NUMBER 0x541F8F0 700 701 #define mmNIC0_QPC0_SECURED_CQ_CONSUMER_INDEX 0x541F8F4 702 703 #define mmNIC0_QPC0_PRIVILEGE_CQ_NUMBER 0x541F8F8 704 705 #define mmNIC0_QPC0_PRIVILEGE_CQ_CONSUMER_INDEX 0x541F8FC 706 707 #define mmNIC0_QPC0_TX_WQ_BASE_ADDR_63_32_0 0x541F900 708 709 #define mmNIC0_QPC0_TX_WQ_BASE_ADDR_63_32_1 0x541F904 710 711 #define mmNIC0_QPC0_TX_WQ_BASE_ADDR_63_32_2 0x541F908 712 713 #define mmNIC0_QPC0_TX_WQ_BASE_ADDR_63_32_3 0x541F90C 714 715 #define mmNIC0_QPC0_TX_WQ_BASE_ADDR_31_0_0 0x541F910 716 717 #define mmNIC0_QPC0_TX_WQ_BASE_ADDR_31_0_1 0x541F914 718 719 #define mmNIC0_QPC0_TX_WQ_BASE_ADDR_31_0_2 0x541F918 720 721 #define mmNIC0_QPC0_TX_WQ_BASE_ADDR_31_0_3 0x541F91C 722 723 #define mmNIC0_QPC0_LOG_MAX_TX_WQ_SIZE_0 0x541F920 724 725 #define mmNIC0_QPC0_LOG_MAX_TX_WQ_SIZE_1 0x541F924 726 727 #define mmNIC0_QPC0_LOG_MAX_TX_WQ_SIZE_2 0x541F928 728 729 #define mmNIC0_QPC0_LOG_MAX_TX_WQ_SIZE_3 0x541F92C 730 731 #define mmNIC0_QPC0_MMU_BYPASS_TX_WQ_0 0x541F930 732 733 #define mmNIC0_QPC0_MMU_BYPASS_TX_WQ_1 0x541F934 734 735 #define mmNIC0_QPC0_MMU_BYPASS_TX_WQ_2 0x541F938 736 737 #define mmNIC0_QPC0_MMU_BYPASS_TX_WQ_3 0x541F93C 738 739 #define mmNIC0_QPC0_RX_WQ_BASE_ADDR_63_32_0 0x541F940 740 741 #define mmNIC0_QPC0_RX_WQ_BASE_ADDR_63_32_1 0x541F944 742 743 #define mmNIC0_QPC0_RX_WQ_BASE_ADDR_63_32_2 0x541F948 744 745 #define mmNIC0_QPC0_RX_WQ_BASE_ADDR_63_32_3 0x541F94C 746 747 #define mmNIC0_QPC0_RX_WQ_BASE_ADDR_31_0_0 0x541F950 748 749 #define mmNIC0_QPC0_RX_WQ_BASE_ADDR_31_0_1 0x541F954 750 751 #define mmNIC0_QPC0_RX_WQ_BASE_ADDR_31_0_2 0x541F958 752 753 #define mmNIC0_QPC0_RX_WQ_BASE_ADDR_31_0_3 0x541F95C 754 755 #define mmNIC0_QPC0_LOG_MAX_RX_WQ_SIZE_0 0x541F960 756 757 #define mmNIC0_QPC0_LOG_MAX_RX_WQ_SIZE_1 0x541F964 758 759 #define mmNIC0_QPC0_LOG_MAX_RX_WQ_SIZE_2 0x541F968 760 761 #define mmNIC0_QPC0_LOG_MAX_RX_WQ_SIZE_3 0x541F96C 762 763 #define mmNIC0_QPC0_MMU_BYPASS_RX_WQ_0 0x541F970 764 765 #define mmNIC0_QPC0_MMU_BYPASS_RX_WQ_1 0x541F974 766 767 #define mmNIC0_QPC0_MMU_BYPASS_RX_WQ_2 0x541F978 768 769 #define mmNIC0_QPC0_MMU_BYPASS_RX_WQ_3 0x541F97C 770 771 #define mmNIC0_QPC0_WQE_MEM_WRITE_AXI_PROT 0x541F980 772 773 #define mmNIC0_QPC0_WQ_UPPER_THRESHOLD 0x541F984 774 775 #define mmNIC0_QPC0_WQ_LOWER_THRESHOLD 0x541F988 776 777 #define mmNIC0_QPC0_WQ_BP_2ARC_ADDR 0x541F98C 778 779 #define mmNIC0_QPC0_WQ_BP_2QMAN_ADDR 0x541F990 780 781 #define mmNIC0_QPC0_WTD_CONFIG 0x541F994 782 783 #define mmNIC0_QPC0_REQTX_ERR_FIFO_PUSH_63_32 0x541F998 784 785 #define mmNIC0_QPC0_REQTX_ERR_FIFO_PUSH_31_0 0x541F99C 786 787 #define mmNIC0_QPC0_REQTX_ERR_QP_STATE_63_32 0x541F9A0 788 789 #define mmNIC0_QPC0_REQTX_ERR_QP_STATE_31_0 0x541F9A4 790 791 #define mmNIC0_QPC0_EVENT_QUE_CONSUMER_INDEX 0x541F9A8 792 793 #define mmNIC0_QPC0_ARM_CQ_NUM 0x541F9AC 794 795 #define mmNIC0_QPC0_ARM_CQ_INDEX 0x541F9B0 796 797 #define mmNIC0_QPC0_QPC_CLOCK_GATE 0x541F9B4 798 799 #define mmNIC0_QPC0_QPC_CLOCK_GATE_DIS 0x541F9B8 800 801 #define mmNIC0_QPC0_CONG_QUE_BASE_ADDR_63_32 0x541F9BC 802 803 #define mmNIC0_QPC0_CONG_QUE_BASE_ADDR_31_7 0x541F9C0 804 805 #define mmNIC0_QPC0_CONG_QUE_LOG_SIZE 0x541F9C4 806 807 #define mmNIC0_QPC0_CONG_QUE_WRITE_INDEX 0x541F9C8 808 809 #define mmNIC0_QPC0_CONG_QUE_PRODUCER_INDEX 0x541F9CC 810 811 #define mmNIC0_QPC0_CONG_QUE_PI_ADDR_63_32 0x541F9D0 812 813 #define mmNIC0_QPC0_CONG_QUE_PI_ADDR_31_7 0x541F9D4 814 815 #define mmNIC0_QPC0_CONG_QUE_CONSUMER_INDEX_CB 0x541F9D8 816 817 #define mmNIC0_QPC0_CONG_QUE_CFG 0x541F9DC 818 819 #define mmNIC0_QPC0_CONG_QUE_CONSUMER_INDEX 0x541F9E0 820 821 #define mmNIC0_QPC0_LINEAR_WQE_STATIC_0 0x541FA00 822 823 #define mmNIC0_QPC0_LINEAR_WQE_STATIC_1 0x541FA04 824 825 #define mmNIC0_QPC0_LINEAR_WQE_STATIC_2 0x541FA08 826 827 #define mmNIC0_QPC0_LINEAR_WQE_STATIC_3 0x541FA0C 828 829 #define mmNIC0_QPC0_LINEAR_WQE_STATIC_4 0x541FA10 830 831 #define mmNIC0_QPC0_LINEAR_WQE_STATIC_5 0x541FA14 832 833 #define mmNIC0_QPC0_LINEAR_WQE_STATIC_6 0x541FA18 834 835 #define mmNIC0_QPC0_LINEAR_WQE_STATIC_7 0x541FA1C 836 837 #define mmNIC0_QPC0_LINEAR_WQE_STATIC_8 0x541FA20 838 839 #define mmNIC0_QPC0_LINEAR_WQE_STATIC_9 0x541FA24 840 841 #define mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_0 0x541FA40 842 843 #define mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_1 0x541FA44 844 845 #define mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_2 0x541FA48 846 847 #define mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_3 0x541FA4C 848 849 #define mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_4 0x541FA50 850 851 #define mmNIC0_QPC0_LINEAR_WQE_DYNAMIC_5 0x541FA54 852 853 #define mmNIC0_QPC0_LINEAR_WQE_QPN 0x541FA58 854 855 #define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_0 0x541FA80 856 857 #define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_1 0x541FA84 858 859 #define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_2 0x541FA88 860 861 #define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_3 0x541FA8C 862 863 #define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_4 0x541FA90 864 865 #define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_5 0x541FA94 866 867 #define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_6 0x541FA98 868 869 #define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_7 0x541FA9C 870 871 #define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_8 0x541FAA0 872 873 #define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_9 0x541FAA4 874 875 #define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_10 0x541FAA8 876 877 #define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_11 0x541FAAC 878 879 #define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_12 0x541FAB0 880 881 #define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_13 0x541FAB4 882 883 #define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_14 0x541FAB8 884 885 #define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_15 0x541FABC 886 887 #define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_16 0x541FAC0 888 889 #define mmNIC0_QPC0_MULTI_STRIDE_WQE_STATIC_17 0x541FAC4 890 891 #define mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_0 0x541FAE0 892 893 #define mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_1 0x541FAE4 894 895 #define mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_2 0x541FAE8 896 897 #define mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_3 0x541FAEC 898 899 #define mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_4 0x541FAF0 900 901 #define mmNIC0_QPC0_MULTI_STRIDE_WQE_DYNAMIC_5 0x541FAF4 902 903 #define mmNIC0_QPC0_MULTI_STRIDE_WQE_QPN 0x541FAF8 904 905 #endif /* ASIC_REG_NIC0_QPC0_REGS_H_ */ 906
