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Searched refs:mmCP_RB_WPTR_POLL_CNTL (Results 1 – 16 of 16) sorted by relevance

/Linux-v6.6/drivers/gpu/drm/amd/amdgpu/
Dmxgpu_vi.c82 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
213 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
Dsi.c536 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
635 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
733 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
813 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
893 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
Dgfx_v9_0.c2674 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL)); in gfx_v9_0_init_gfx_power_gating()
2677 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data); in gfx_v9_0_init_gfx_power_gating()
4778 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); in gfx_v9_0_update_3d_clock_gating()
4782 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); in gfx_v9_0_update_3d_clock_gating()
4832 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); in gfx_v9_0_update_coarse_grain_clock_gating()
4836 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); in gfx_v9_0_update_coarse_grain_clock_gating()
Dgfx_v8_0.c303 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
466 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
567 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
673 mmCP_RB_WPTR_POLL_CNTL, 0xffffffff, 0x00900100,
Dgfx_v7_0.c3855 data = RREG32(mmCP_RB_WPTR_POLL_CNTL); in gfx_v7_0_init_gfx_cgpg()
3858 WREG32(mmCP_RB_WPTR_POLL_CNTL, data); in gfx_v7_0_init_gfx_cgpg()
Dgfx_v10_0.c7639 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); in gfx_v10_0_update_3d_clock_gating()
7643 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); in gfx_v10_0_update_3d_clock_gating()
7699 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL); in gfx_v10_0_update_coarse_grain_clock_gating()
7703 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data); in gfx_v10_0_update_coarse_grain_clock_gating()
/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_d.h524 #define mmCP_RB_WPTR_POLL_CNTL 0x21C2 macro
Dgfx_7_0_d.h513 #define mmCP_RB_WPTR_POLL_CNTL 0x21c2 macro
Dgfx_7_2_d.h526 #define mmCP_RB_WPTR_POLL_CNTL 0x21c2 macro
Dgfx_8_0_d.h579 #define mmCP_RB_WPTR_POLL_CNTL 0x21c2 macro
Dgfx_8_1_d.h579 #define mmCP_RB_WPTR_POLL_CNTL 0x21c2 macro
/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h217 #define mmCP_RB_WPTR_POLL_CNTL … macro
Dgc_9_1_offset.h217 #define mmCP_RB_WPTR_POLL_CNTL … macro
Dgc_9_2_1_offset.h211 #define mmCP_RB_WPTR_POLL_CNTL … macro
Dgc_10_1_0_offset.h2219 #define mmCP_RB_WPTR_POLL_CNTL … macro
Dgc_10_3_0_offset.h2302 #define mmCP_RB_WPTR_POLL_CNTL … macro