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Searched refs:mmCP_RB0_WPTR (Results 1 – 15 of 15) sorted by relevance

/Linux-v6.6/drivers/gpu/drm/amd/amdgpu/
Dgfx_v6_0.c2079 WREG32(mmCP_RB0_WPTR, ring->wptr); in gfx_v6_0_cp_gfx_resume()
2112 return RREG32(mmCP_RB0_WPTR); in gfx_v6_0_ring_get_wptr()
2125 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); in gfx_v6_0_ring_set_wptr_gfx()
2126 (void)RREG32(mmCP_RB0_WPTR); in gfx_v6_0_ring_set_wptr_gfx()
Dgfx_v7_0.c2560 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); in gfx_v7_0_cp_gfx_resume()
2595 return RREG32(mmCP_RB0_WPTR); in gfx_v7_0_ring_get_wptr_gfx()
2602 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); in gfx_v7_0_ring_set_wptr_gfx()
2603 (void)RREG32(mmCP_RB0_WPTR); in gfx_v7_0_ring_set_wptr_gfx()
Dgfx_v8_0.c4265 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); in gfx_v8_0_cp_gfx_resume()
6024 return RREG32(mmCP_RB0_WPTR); in gfx_v8_0_ring_get_wptr_gfx()
6036 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); in gfx_v8_0_ring_set_wptr_gfx()
6037 (void)RREG32(mmCP_RB0_WPTR); in gfx_v8_0_ring_set_wptr_gfx()
Dgfx_v9_0.c3110 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); in gfx_v9_0_cp_gfx_resume()
5077 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); in gfx_v9_0_ring_get_wptr_gfx()
5093 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); in gfx_v9_0_ring_set_wptr_gfx()
Dgfx_v10_0.c6116 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); in gfx_v10_0_cp_gfx_resume()
8154 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); in gfx_v10_0_ring_get_wptr_gfx()
8198 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, in gfx_v10_0_ring_set_wptr_gfx()
/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_6_0_d.h499 #define mmCP_RB0_WPTR 0x3045 macro
Dgfx_7_0_d.h214 #define mmCP_RB0_WPTR 0x3045 macro
Dgfx_7_2_d.h214 #define mmCP_RB0_WPTR 0x3045 macro
Dgfx_8_0_d.h238 #define mmCP_RB0_WPTR 0x3045 macro
Dgfx_8_1_d.h239 #define mmCP_RB0_WPTR 0x3045 macro
/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h2420 #define mmCP_RB0_WPTR macro
Dgc_9_1_offset.h2697 #define mmCP_RB0_WPTR macro
Dgc_9_2_1_offset.h2635 #define mmCP_RB0_WPTR macro
Dgc_10_1_0_offset.h4761 #define mmCP_RB0_WPTR macro
Dgc_10_3_0_offset.h4414 #define mmCP_RB0_WPTR macro