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Searched refs:mmCP_HQD_PQ_WPTR_HI (Results 1 – 10 of 10) sorted by relevance

/Linux-v6.6/drivers/gpu/drm/amd/amdgpu/
Damdgpu_amdkfd_gfx_v10_3.c213 reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) in hqd_load_v10_3()
251 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, in hqd_load_v10_3()
348 reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) in hqd_dump_v10_3()
Damdgpu_amdkfd_gfx_v10.c227 reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) in kgd_hqd_load()
265 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, in kgd_hqd_load()
362 reg <= SOC15_REG_OFFSET(GC, 0, mmCP_HQD_PQ_WPTR_HI); reg++) in kgd_hqd_dump()
Damdgpu_amdkfd_gfx_v9.c241 reg <= SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_HI); reg++) in kgd_gfx_v9_hqd_load()
280 WREG32_RLC(SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_HI), in kgd_gfx_v9_hqd_load()
375 reg <= SOC15_REG_OFFSET(GC, GET_INST(GC, inst), mmCP_HQD_PQ_WPTR_HI); reg++) in kgd_gfx_v9_hqd_dump()
Dgfx_v9_0.c3404 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI, in gfx_v9_0_kiq_init_register()
3463 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI, in gfx_v9_0_kiq_init_register()
3515 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_PQ_WPTR_HI, 0); in gfx_v9_0_kiq_fini_register()
Dgfx_v10_0.c6646 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, in gfx_v10_0_kiq_init_register()
6709 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, in gfx_v10_0_kiq_init_register()
/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h2933 #define mmCP_HQD_PQ_WPTR_HI macro
Dgc_9_1_offset.h3161 #define mmCP_HQD_PQ_WPTR_HI macro
Dgc_9_2_1_offset.h3117 #define mmCP_HQD_PQ_WPTR_HI macro
Dgc_10_1_0_offset.h5415 #define mmCP_HQD_PQ_WPTR_HI macro
Dgc_10_3_0_offset.h5050 #define mmCP_HQD_PQ_WPTR_HI macro