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Searched refs:mmCP_CPC_IC_BASE_CNTL (Results 1 – 10 of 10) sorted by relevance

/Linux-v6.6/drivers/gpu/drm/amd/pm/powerplay/smumgr/
Dsmu8_smumgr.c198 mmCP_CPC_IC_BASE_CNTL); in smu8_load_mec_firmware()
204 cgs_write_register(hwmgr->device, mmCP_CPC_IC_BASE_CNTL, tmp); in smu8_load_mec_firmware()
/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_8_0_d.h348 #define mmCP_CPC_IC_BASE_CNTL 0x30bb macro
Dgfx_8_1_d.h348 #define mmCP_CPC_IC_BASE_CNTL 0x30bb macro
/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_9_0_offset.h2607 #define mmCP_CPC_IC_BASE_CNTL macro
Dgc_9_1_offset.h2877 #define mmCP_CPC_IC_BASE_CNTL macro
Dgc_9_2_1_offset.h2811 #define mmCP_CPC_IC_BASE_CNTL macro
Dgc_10_1_0_offset.h10281 #define mmCP_CPC_IC_BASE_CNTL macro
Dgc_10_3_0_offset.h10003 #define mmCP_CPC_IC_BASE_CNTL macro
/Linux-v6.6/drivers/gpu/drm/amd/amdgpu/
Dgfx_v10_0.c6275 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL); in gfx_v10_0_cp_compute_load_microcode()
6279 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); in gfx_v10_0_cp_compute_load_microcode()
Dgfx_v9_0.c3187 WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp); in gfx_v9_0_cp_compute_load_microcode()