Home
last modified time | relevance | path

Searched refs:mmCGTS_SA0_QUAD0_SM_CTRL_REG_BASE_IDX (Results 1 – 2 of 2) sorted by relevance

/Linux-v6.6/drivers/gpu/drm/amd/include/asic_reg/gc/
Dgc_10_1_0_offset.h9896 #define mmCGTS_SA0_QUAD0_SM_CTRL_REG_BASE_IDX … macro
/Linux-v6.6/drivers/gpu/drm/amd/amdgpu/
Dgfx_v10_0.c7841 reg_idx = adev->reg_offset[GC_HWIP][0][mmCGTS_SA0_QUAD0_SM_CTRL_REG_BASE_IDX] + in gfx_v10_0_apply_medium_grain_clock_gating_workaround()