Searched refs:min_fill_clk_mhz (Results 1 – 15 of 15) sorted by relevance
468 …ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MI… in build_watermark_ranges()483 …ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MI… in build_watermark_ranges()497 ranges->reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; in build_watermark_ranges()504 ranges->writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; in build_watermark_ranges()
77 uint16_t min_fill_clk_mhz; member
490 ranges->reader_wm_sets[i].min_fill_clk_mhz * 1000; in pp_rv_set_wm_ranges()502 ranges->writer_wm_sets[i].min_fill_clk_mhz * 1000; in pp_rv_set_wm_ranges()
1332 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; in set_wm_ranges()1347 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; in set_wm_ranges()1354 ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; in set_wm_ranges()
421 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; in smu_v13_0_5_set_watermarks_table()431 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; in smu_v13_0_5_set_watermarks_table()
665 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; in smu_v13_0_4_set_watermarks_table()675 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; in smu_v13_0_4_set_watermarks_table()
512 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; in yellow_carp_set_watermarks_table()522 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; in yellow_carp_set_watermarks_table()
394 …ranges->reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_… in dcn301_fpu_set_wm_ranges()
1528 ranges.reader_wm_sets[0].min_fill_clk_mhz = min_fclk_khz / 1000; in dcn_bw_notify_pplib_of_wm_ranges()1531 ranges.writer_wm_sets[0].min_fill_clk_mhz = socclk_khz / 1000; in dcn_bw_notify_pplib_of_wm_ranges()1540 ranges.reader_wm_sets[0].min_fill_clk_mhz = 800; in dcn_bw_notify_pplib_of_wm_ranges()1543 ranges.writer_wm_sets[0].min_fill_clk_mhz = 200; in dcn_bw_notify_pplib_of_wm_ranges()
1062 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; in renoir_set_watermarks_table()1074 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; in renoir_set_watermarks_table()
2570 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; in dcn20_resource_construct()2586 ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; in dcn20_resource_construct()2593 ranges.writer_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN; in dcn20_resource_construct()
1643 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; in vangogh_set_watermarks_table()1653 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; in vangogh_set_watermarks_table()
2138 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; in navi10_set_watermarks_table()2148 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; in navi10_set_watermarks_table()
1838 clock_ranges->reader_wm_sets[i].min_fill_clk_mhz; in sienna_cichlid_set_watermarks_table()1848 clock_ranges->writer_wm_sets[i].min_fill_clk_mhz; in sienna_cichlid_set_watermarks_table()
2036 …ranges->reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_… in dcn20_fpu_set_wm_ranges()
