Searched refs:max_dppclk_vmid0p72 (Results 1 – 2 of 2) sorted by relevance
124 float max_dppclk_vmid0p72; member562 float max_dppclk_vmid0p72; /*MHz*/ member
89 .max_dppclk_vmid0p72 = 626, /* MHz, = 3600/5.75 */793 v->max_dppclk_vmid0p72 = dc->dcn_soc->max_dppclk_vmid0p72; in dcn_validate_bandwidth()881 v->max_dppclk[1] = v->max_dppclk_vmid0p72; in dcn_validate_bandwidth()1185 (int)(dc->dcn_soc->max_dppclk_vmid0p72 * 1000); in dcn_validate_bandwidth()1359 } else if (clocks_in_khz > dc->dcn_soc->max_dppclk_vmid0p72*1000) { in dcn_find_normalized_clock_vdd_Level()1614 dc->dcn_soc->max_dppclk_vmid0p72 * 1000, in dcn_bw_sync_calcs_and_dml()
