Searched refs:masters (Results 1 – 25 of 72) sorted by relevance
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65 struct fake_master_window masters[FAKE_MAX_MASTER]; member317 bridge->masters[i].enabled = enabled; in fake_master_set()318 bridge->masters[i].vme_base = vme_base; in fake_master_set()319 bridge->masters[i].size = size; in fake_master_set()320 bridge->masters[i].aspace = aspace; in fake_master_set()321 bridge->masters[i].cycle = cycle; in fake_master_set()322 bridge->masters[i].dwidth = dwidth; in fake_master_set()348 *enabled = bridge->masters[i].enabled; in __fake_master_get()349 *vme_base = bridge->masters[i].vme_base; in __fake_master_get()350 *size = bridge->masters[i].size; in __fake_master_get()[all …]
49 association of masters to be configured. Note that an IOMMU can by design56 - #iommu-cells = <4>: Some IOMMU devices allow the DMA window for masters to70 Devices that access memory through an IOMMU are called masters. A device can91 - pasid-num-bits: Some masters support multiple address spaces for DMA, by105 Firmware has to opt-in stalling, because most buses and masters don't108 won't work in systems and masters that haven't been designed for148 * have sufficient information to distinguish between masters.151 * all masters at any given point in time.
1 What: /sys/class/stm/<stm>/masters24 assigned masters.
34 What: /config/stp-policy/<device>.<policy>/<node>/masters38 Range of masters from which to allocate for users of this node.
1 What: /sys/bus/intel_th/devices/<intel_th_id>-gth/masters/*5 Description: (RW) Configure output ports for STP masters. Writing -1
6 Reading the file will give you a list of masters which can be
11 these masters and channels are statically allocated to certain23 master 7 channel 15, while arbitrary user applications can use masters28 identifiers to ranges of masters and channels. If these rules (policy)33 have a name (string identifier) and a range of masters and channels41 channels masters42 $ cat /config/stp-policy/dummy_stm.my-policy/user/masters48 masters 48 through 63 and channel allocation pool has channels 0
37 GTH allows directing different STP masters into different output ports38 via its "masters" attribute group. More detailed GTH interface79 $ echo 0 > /sys/bus/intel_th/devices/0-gth/masters/33
12 - dma-masters: phandle pointing to the DMA controller41 dma-masters = <&dmac>;
10 - dma-masters: phandle pointing to the DMA controller55 dma-masters = <&sdma>;
11 FSI masters may require their own DT nodes (to describe the master HW itself);15 Under the masters' nodes, we can describe the bus topology using nodes to43 FSI masters62 masters that may be present on the bus.
13 functions (eg, external FSI masters)
4 The AST2600 contains two identical FSI masters. They share a clock and have a
15 functions (eg, external FSI masters)
9 obj-y += masters/ slaves/
29 source "drivers/w1/masters/Kconfig"
13 masters/index
26 list current bus masters92 w1_netlink_msg) plus number of masters multiplied by 4)94 number of masters multiplied by 4 (u32 size))
25 - i2c-parent: List of phandles of I2C masters available for selection. The first134 - the i2c masters must have their status "disabled". This driver will
5 peripherals classified as masters.
45 struct stp_master *masters[]; member
177 int i, ret, masters = 0; in pm8xxx_irq_handler() local186 masters = root >> 1; in pm8xxx_irq_handler()190 if (masters & (1 << i)) in pm8xxx_irq_handler()
113 dma-masters = <2>;126 dma-masters = <2>;
116 dma-masters = <&dma0 &dma1>;299 dma-masters = <1>;313 dma-masters = <1>;
383 This can be achieved by placing the DSA masters under a LAG interface (bonding385 on the CPU ports facing the physical DSA masters that constitute the LAG slave389 the switch must mark all the links between CPU ports and their DSA masters393 configure the system for the switch to use other masters.447 static user to CPU port assignment with LAG between DSA masters. It is not455 Physical DSA masters are allowed to join and leave at any time a LAG interface
