Searched refs:link_level (Results 1 – 3 of 3) sorted by relevance
574 uint32_t link_level; in smu_v13_0_7_set_default_dpm_table() local684 for (link_level = 0; link_level < NUM_LINK_LEVELS; link_level++) { in smu_v13_0_7_set_default_dpm_table()685 if (!skutable->PcieGenSpeed[link_level] && in smu_v13_0_7_set_default_dpm_table()686 !skutable->PcieLaneCount[link_level] && in smu_v13_0_7_set_default_dpm_table()687 !skutable->LclkFreq[link_level]) in smu_v13_0_7_set_default_dpm_table()691 skutable->PcieGenSpeed[link_level]; in smu_v13_0_7_set_default_dpm_table()693 skutable->PcieLaneCount[link_level]; in smu_v13_0_7_set_default_dpm_table()695 skutable->LclkFreq[link_level]; in smu_v13_0_7_set_default_dpm_table()
576 uint32_t link_level; in smu_v13_0_0_set_default_dpm_table() local695 for (link_level = 0; link_level < NUM_LINK_LEVELS; link_level++) { in smu_v13_0_0_set_default_dpm_table()696 if (!skutable->PcieGenSpeed[link_level] && in smu_v13_0_0_set_default_dpm_table()697 !skutable->PcieLaneCount[link_level] && in smu_v13_0_0_set_default_dpm_table()698 !skutable->LclkFreq[link_level]) in smu_v13_0_0_set_default_dpm_table()702 skutable->PcieGenSpeed[link_level]; in smu_v13_0_0_set_default_dpm_table()704 skutable->PcieLaneCount[link_level]; in smu_v13_0_0_set_default_dpm_table()706 skutable->LclkFreq[link_level]; in smu_v13_0_0_set_default_dpm_table()
1818 int link_level; in nix_reset_tx_linkcfg() local1828 link_level = rvu_read64(rvu, blkaddr, NIX_AF_PSE_CHANNEL_LEVEL) & 0x01 ? in nix_reset_tx_linkcfg()1830 if (lvl != link_level) in nix_reset_tx_linkcfg()
