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Searched refs:lane_count (Results 1 – 25 of 74) sorted by relevance

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/Linux-v6.6/drivers/gpu/drm/amd/display/dc/link/protocols/
Dlink_dp_training_fixed_vs_pe_retimer.c75 uint8_t lane_count) in dp_fixed_vs_pe_set_retimer_lane_settings() argument
82 for (lane = 0; lane < lane_count; lane++) { in dp_fixed_vs_pe_set_retimer_lane_settings()
252 lt_settings->link_settings.lane_count; in dp_perform_fixed_vs_pe_training_sequence_legacy()
291 lt_settings->link_settings.lane_count, in dp_perform_fixed_vs_pe_training_sequence_legacy()
296 if (lt_settings->link_settings.lane_count == LANE_COUNT_FOUR) { in dp_perform_fixed_vs_pe_training_sequence_legacy()
317 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in dp_perform_fixed_vs_pe_training_sequence_legacy() local
368 for (lane = 0; lane < lane_count; lane++) { in dp_perform_fixed_vs_pe_training_sequence_legacy()
406 if (dp_is_cr_done(lane_count, dpcd_lane_status)) { in dp_perform_fixed_vs_pe_training_sequence_legacy()
439 status = dp_get_cr_failure(lane_count, dpcd_lane_status); in dp_perform_fixed_vs_pe_training_sequence_legacy()
447 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in dp_perform_fixed_vs_pe_training_sequence_legacy() local
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Dlink_dp_capability.c66 enum dc_lane_count lane_count; member
101 .lane_count = LANE_COUNT_ONE,
425 static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count) in reached_minimum_lane_count() argument
427 return lane_count <= LANE_COUNT_ONE; in reached_minimum_lane_count()
435 static enum dc_lane_count reduce_lane_count(enum dc_lane_count lane_count) in reduce_lane_count() argument
437 switch (lane_count) { in reduce_lane_count()
484 static enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count) in increase_lane_count() argument
486 switch (lane_count) { in increase_lane_count()
539 if (dp_lt_fallbacks[cur_idx].lane_count == cur->lane_count && in decide_fallback_link_setting_max_bw_policy()
549 if (dp_lt_fallbacks[next_idx].lane_count > max->lane_count || in decide_fallback_link_setting_max_bw_policy()
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Dlink_dp_training_8b_10b.c103 lt_settings->link_settings.lane_count = link_setting->lane_count; in decide_8b_10b_training_settings()
163 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in perform_8b_10b_clock_recovery_sequence() local
228 if (dp_is_cr_done(lane_count, dpcd_lane_status)) { in perform_8b_10b_clock_recovery_sequence()
267 return dp_get_cr_failure(lane_count, dpcd_lane_status); in perform_8b_10b_clock_recovery_sequence()
279 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in perform_8b_10b_channel_equalization_sequence() local
334 if (!dp_is_cr_done(lane_count, dpcd_lane_status)) in perform_8b_10b_channel_equalization_sequence()
340 if (dp_is_ch_eq_done(lane_count, dpcd_lane_status) && in perform_8b_10b_channel_equalization_sequence()
341 dp_is_symbol_locked(lane_count, dpcd_lane_status) && in perform_8b_10b_channel_equalization_sequence()
Dlink_dp_training_dpia.c298 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in dpia_training_cr_non_transparent() local
403 if (dp_is_cr_done(lane_count, dpcd_lane_status)) { in dpia_training_cr_non_transparent()
409 result = dp_get_cr_failure(lane_count, dpcd_lane_status); in dpia_training_cr_non_transparent()
468 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in dpia_training_cr_transparent() local
511 if (dp_is_cr_done(lane_count, dpcd_lane_status)) { in dpia_training_cr_transparent()
517 result = dp_get_cr_failure(lane_count, dpcd_lane_status); in dpia_training_cr_transparent()
623 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in dpia_training_eq_non_transparent() local
717 if (!dp_is_cr_done(lane_count, dpcd_lane_status)) { in dpia_training_eq_non_transparent()
722 if (dp_is_ch_eq_done(lane_count, dpcd_lane_status) && in dpia_training_eq_non_transparent()
723 dp_is_symbol_locked(link->cur_link_settings.lane_count, dpcd_lane_status) && in dpia_training_eq_non_transparent()
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Dlink_dp_training.c172 lt_settings->link_settings.lane_count, in dp_log_training_result()
313 for (lane = 1; lane < lt_settings->link_settings.lane_count; lane++) { in maximize_lane_settings()
463 (uint32_t)(lt_settings->link_settings.lane_count); in dp_is_max_vs_reached()
530 for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) { in dp_check_link_loss_status()
589 (uint32_t)(link_training_setting->link_settings.lane_count); in dp_get_lane_status_and_lane_adjust()
1045 lt_settings->link_settings.lane_count; in dpcd_set_link_settings()
1091 lt_settings->link_settings.lane_count, in dpcd_set_link_settings()
1101 lt_settings->link_settings.lane_count, in dpcd_set_link_settings()
1126 link_training_setting->link_settings.lane_count); in dpcd_set_lane_settings()
1195 size_in_bytes = lt_settings->link_settings.lane_count * in dpcd_set_lt_pattern_and_lane_settings()
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Dlink_dp_irq_handler.c57 if (link->cur_link_settings.lane_count == 0) in dp_parse_link_loss_status()
63 for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) { in dp_parse_link_loss_status()
262 pipes[i]->link_config.dp_link_settings.lane_count = in dp_handle_link_loss()
263 link->verified_link_cap.lane_count; in dp_handle_link_loss()
354 if ((link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) || in dp_should_allow_hpd_rx_irq()
/Linux-v6.6/drivers/gpu/drm/bridge/analogix/
Danalogix_dp_core.c262 int lane, lane_count, pll_tries, retval; in analogix_dp_link_start() local
264 lane_count = dp->link_train.lane_count; in analogix_dp_link_start()
269 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
274 analogix_dp_set_lane_count(dp, dp->link_train.lane_count); in analogix_dp_link_start()
278 buf[1] = dp->link_train.lane_count; in analogix_dp_link_start()
290 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
316 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
321 lane_count); in analogix_dp_link_start()
336 static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count) in analogix_dp_clock_recovery_ok() argument
341 for (lane = 0; lane < lane_count; lane++) { in analogix_dp_clock_recovery_ok()
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/Linux-v6.6/drivers/gpu/drm/i915/display/
Dintel_dp_link_training.c330 lane = min(lane, crtc_state->lane_count - 1); in intel_dp_get_lane_adjust_tx_ffe_preset()
333 for (lane = 0; lane < crtc_state->lane_count; lane++) in intel_dp_get_lane_adjust_tx_ffe_preset()
353 lane = min(lane, crtc_state->lane_count - 1); in intel_dp_get_lane_adjust_vswing_preemph()
358 for (lane = 0; lane < crtc_state->lane_count; lane++) { in intel_dp_get_lane_adjust_vswing_preemph()
426 crtc_state->lane_count, in intel_dp_get_adjust_train()
433 crtc_state->lane_count, in intel_dp_get_adjust_train()
467 memcpy(buf + 1, intel_dp->train_set, crtc_state->lane_count); in intel_dp_set_link_train()
468 len = crtc_state->lane_count + 1; in intel_dp_set_link_train()
538 crtc_state->lane_count, in intel_dp_set_signal_levels()
545 crtc_state->lane_count, in intel_dp_set_signal_levels()
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Dintel_dp.h42 int link_rate, int lane_count);
44 int link_rate, u8 lane_count);
111 u32 link_clock, u32 lane_count,
122 static inline unsigned int intel_dp_unused_lane_mask(int lane_count) in intel_dp_unused_lane_mask() argument
124 return ~((1 << lane_count) - 1) & 0xf; in intel_dp_unused_lane_mask()
Dintel_dpio_phy.c573 bxt_ddi_phy_calc_lane_lat_optim_mask(u8 lane_count) in bxt_ddi_phy_calc_lane_lat_optim_mask() argument
575 switch (lane_count) { in bxt_ddi_phy_calc_lane_lat_optim_mask()
583 MISSING_CASE(lane_count); in bxt_ddi_phy_calc_lane_lat_optim_mask()
705 if (crtc_state->lane_count > 2) { in chv_set_phy_signal_level()
718 if (crtc_state->lane_count > 2) { in chv_set_phy_signal_level()
726 for (i = 0; i < crtc_state->lane_count; i++) { in chv_set_phy_signal_level()
734 for (i = 0; i < crtc_state->lane_count; i++) { in chv_set_phy_signal_level()
757 for (i = 0; i < crtc_state->lane_count; i++) { in chv_set_phy_signal_level()
771 if (crtc_state->lane_count > 2) { in chv_set_phy_signal_level()
797 if (crtc_state->lane_count > 2) { in chv_data_lane_soft_reset()
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Dvlv_dsi.c52 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count, in txbyteclkhs() argument
56 8 * 100), lane_count); in txbyteclkhs()
60 static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count, in pixels_from_txbyteclkhs() argument
63 return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100), in pixels_from_txbyteclkhs()
1016 unsigned int lane_count = intel_dsi->lane_count; in bxt_dsi_get_pipe_config() local
1068 hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count, in bxt_dsi_get_pipe_config()
1070 hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count, in bxt_dsi_get_pipe_config()
1072 hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count, in bxt_dsi_get_pipe_config()
1121 hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count, in bxt_dsi_get_pipe_config()
1123 hsync_sw = txbyteclkhs(hsync_sw, bpp, lane_count, in bxt_dsi_get_pipe_config()
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Dintel_combo_phy.c263 int lane_count, bool lane_reversal) in intel_combo_phy_power_up_lanes() argument
270 switch (lane_count) { in intel_combo_phy_power_up_lanes()
281 MISSING_CASE(lane_count); in intel_combo_phy_power_up_lanes()
288 switch (lane_count) { in intel_combo_phy_power_up_lanes()
298 MISSING_CASE(lane_count); in intel_combo_phy_power_up_lanes()
Dvlv_dsi_pll.c48 int lane_count) in dsi_clk_from_pclk() argument
55 dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count); in dsi_clk_from_pclk()
168 return DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, bpp); in vlv_dsi_pclk()
183 intel_dsi->lane_count); in vlv_dsi_pll_compute()
349 return DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, bpp); in bxt_dsi_pclk()
488 intel_dsi->lane_count); in bxt_dsi_pll_compute()
Dintel_dp.c591 u8 lane_count) in intel_dp_link_params_valid() argument
602 if (lane_count == 0 || in intel_dp_link_params_valid()
603 lane_count > intel_dp_max_lane_count(intel_dp)) in intel_dp_link_params_valid()
611 u8 lane_count) in intel_dp_can_link_train_fallback_for_edp() argument
619 max_rate = intel_dp_max_data_rate(link_rate, lane_count); in intel_dp_can_link_train_fallback_for_edp()
627 int link_rate, u8 lane_count) in intel_dp_get_link_train_fallback_values() argument
655 lane_count)) { in intel_dp_get_link_train_fallback_values()
661 intel_dp->max_link_lane_count = lane_count; in intel_dp_get_link_train_fallback_values()
662 } else if (lane_count > 1) { in intel_dp_get_link_train_fallback_values()
666 lane_count >> 1)) { in intel_dp_get_link_train_fallback_values()
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Dintel_combo_phy.h18 int lane_count, bool lane_reversal);
Dintel_crtc_state_dump.c31 const char *id, unsigned int lane_count, in intel_dump_m_n_config() argument
38 id, lane_count, in intel_dump_m_n_config()
256 pipe_config->lane_count, in intel_crtc_state_dump()
259 pipe_config->lane_count, in intel_crtc_state_dump()
/Linux-v6.6/drivers/gpu/drm/msm/dp/
Ddp_panel.h96 static inline bool is_lane_count_valid(u32 lane_count) in is_lane_count_valid() argument
98 return (lane_count == 1 || in is_lane_count_valid()
99 lane_count == 2 || in is_lane_count_valid()
100 lane_count == 4); in is_lane_count_valid()
/Linux-v6.6/drivers/gpu/drm/gma500/
Dcdv_intel_dp.c262 uint8_t lane_count; member
898 int lane_count, clock; in cdv_intel_dp_mode_fixup() local
911 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { in cdv_intel_dp_mode_fixup()
913 int link_avail = cdv_intel_dp_max_data_rate(cdv_intel_dp_link_clock(bws[clock]), lane_count); in cdv_intel_dp_mode_fixup()
917 intel_dp->lane_count = lane_count; in cdv_intel_dp_mode_fixup()
921 intel_dp->link_bw, intel_dp->lane_count, in cdv_intel_dp_mode_fixup()
929 intel_dp->lane_count = max_lane_count; in cdv_intel_dp_mode_fixup()
934 intel_dp->link_bw, intel_dp->lane_count, in cdv_intel_dp_mode_fixup()
991 int lane_count = 4, bpp = 24; in cdv_intel_dp_set_m_n() local
1008 lane_count = intel_dp->lane_count; in cdv_intel_dp_set_m_n()
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/Linux-v6.6/drivers/gpu/drm/bridge/
Dparade-ps8622.c54 u32 lane_count; member
184 err = ps8622_set(cl, 0x01, 0x21, 0x80 | ps8622->lane_count); in ps8622_send_config()
490 &ps8622->lane_count)) { in ps8622_probe()
491 ps8622->lane_count = ps8622->max_lane_count; in ps8622_probe()
492 } else if (ps8622->lane_count > ps8622->max_lane_count) { in ps8622_probe()
495 ps8622->lane_count = ps8622->max_lane_count; in ps8622_probe()
Dite-it6505.c428 u8 lane_count; member
819 switch (it6505->lane_count) { in it6505_lane_termination_on()
831 switch (it6505->lane_count) { in it6505_lane_termination_on()
863 GENMASK(7, 8 - it6505->lane_count) : in it6505_lane_power_on()
864 GENMASK(3 + it6505->lane_count, 4)) | in it6505_lane_power_on()
1181 it6505->lane_count = MAX_LANE_COUNT; in it6505_variable_config()
1479 it6505->lane_count = link->num_lanes; in it6505_parse_link_capabilities()
1481 it6505->lane_count); in it6505_parse_link_capabilities()
1482 it6505->lane_count = min_t(int, it6505->lane_count, in it6505_parse_link_capabilities()
1555 (it6505->lane_count - 1) << 1); in it6505_lane_count_setup()
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/Linux-v6.6/drivers/gpu/drm/amd/display/dc/dcn31/
Ddcn31_dio_link_encoder.c475 dpia_control.lanenum = (uint8_t)link_settings->lane_count; in dcn31_link_encoder_enable_dp_output()
522 dpia_control.lanenum = (uint8_t)link_settings->lane_count; in dcn31_link_encoder_enable_dp_mst_output()
658 link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count); in dcn31_link_encoder_get_max_link_cap()
680 link_settings->lane_count = MIN(LANE_COUNT_TWO, link_settings->lane_count); in dcn31_link_encoder_get_max_link_cap()
/Linux-v6.6/drivers/gpu/drm/amd/display/dc/link/hwss/
Dlink_hwss_hpo_fixed_vs_pe_retimer_dp.c104 if (link->cur_link_settings.lane_count == LANE_COUNT_FOUR) in dp_hpo_fixed_vs_pe_retimer_program_override_test_pattern()
111 if (link->cur_link_settings.lane_count == LANE_COUNT_FOUR) in dp_hpo_fixed_vs_pe_retimer_program_override_test_pattern()
191 if (link_settings->lane_count == LANE_COUNT_FOUR) in enable_hpo_fixed_vs_pe_retimer_dp_link_output()
/Linux-v6.6/drivers/gpu/drm/mediatek/
Dmtk_dp.c74 int lane_count; member
1149 u32 link_rate, int lane_count) in mtk_dp_phy_configure() argument
1156 .lanes = lane_count, in mtk_dp_phy_configure()
1320 mtk_dp->train_info.lane_count = mtk_dp->max_lanes; in mtk_dp_initialize_priv_data()
1342 switch (mtk_dp->train_info.lane_count) { in mtk_dp_sdp_set_down_cnt_init()
1375 switch (mtk_dp->train_info.lane_count) { in mtk_dp_sdp_set_down_cnt_init_in_hblank()
1401 mtk_dp->train_info.lane_count / in mtk_dp_setup_tu()
1697 u8 lane_count, link_rate, train_limit, max_link_rate; in mtk_dp_training() local
1702 lane_count = min_t(u8, mtk_dp->max_lanes, in mtk_dp_training()
1715 ret = mtk_dp_train_setting(mtk_dp, link_rate, lane_count); in mtk_dp_training()
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/Linux-v6.6/drivers/gpu/drm/amd/display/amdgpu_dm/
Damdgpu_dm_debugfs.c207 link->cur_link_settings.lane_count, in dp_link_settings_read()
214 link->verified_link_cap.lane_count, in dp_link_settings_read()
221 link->reported_link_cap.lane_count, in dp_link_settings_read()
228 link->preferred_link_setting.lane_count, in dp_link_settings_read()
328 prefer_link_settings.lane_count = param[0]; in dp_link_settings_write()
462 prefer_link_settings.lane_count = param[0]; in dp_mst_link_setting()
657 link_lane_settings.link_settings.lane_count = in dp_phy_settings_write()
658 link->preferred_link_setting.lane_count; in dp_phy_settings_write()
664 link_lane_settings.link_settings.lane_count = in dp_phy_settings_write()
665 link->cur_link_settings.lane_count; in dp_phy_settings_write()
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/Linux-v6.6/drivers/gpu/drm/amd/display/dc/dcn201/
Ddcn201_link_encoder.c63 if (!value1 && !value2 && link_settings->lane_count > LANE_COUNT_TWO) in dcn201_link_encoder_get_max_link_cap()
64 link_settings->lane_count = LANE_COUNT_TWO; in dcn201_link_encoder_get_max_link_cap()

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