Searched refs:l6 (Results 1 – 25 of 120) sorted by relevance
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21 rdpr %tstate, %l623 andn %l6, TSTATE_CWP, %l624 wrpr %l6, %l7, %tstate25 rdpr %tpc, %l6
133 sethi %hi(num_kernel_image_mappings), %l6134 lduw [%l6 + %lo(num_kernel_image_mappings)], %l6210 cmp %l5, %l6225 sethi %hi(num_kernel_image_mappings), %l6226 lduw [%l6 + %lo(num_kernel_image_mappings)], %l6246 cmp %l5, %l6
92 mov %g6, %l6112 sth %l5, [%l6 + TI_SYS_NOERROR]190 mov %l6, %g6197 ldub [%l6 + TI_FPDEPTH], %l5198 add %l6, TI_FPSAVED + 1, %l4203 sth %l5, [%l6 + TI_SYS_NOERROR]
89 ld [%l5 + %lo(pdma_size)], %l699 sub %l6, 0x1, %l6103 orcc %g0, %l6, %g0114 orcc %g0, %l6, %g0124 st %l6, [%l5 + %lo(pdma_size)]156 st %l6, [%l7 + %lo(pdma_size)]169 st %l6, [%l5 + %lo(pdma_size)]339 clr %l6385 clr %l6426 clr %l6[all …]
139 set KERNBASE, %l6144 mov 0, %l6154 sub %g1, %l6, %g1 ! translate to physical155 sub %g3, %l6, %g3 ! translate to physical166 sub %g3, %l6, %g3180 cmp %l6, 0195 sub %o0, %l6, %o0732 sub %g3, %l2, %l6733 add %o0, %l6, %o0740 add %l5, %l6, %l5
84 ldx [%l0 + HVTRAMP_DESCR_THREAD_REG], %l6106 mov %l6, %g6
330 add %g6, TI_FPSAVED, %l6331 ldub [%l6 + %o0], %l2337 and %l2, FPRS_DL, %l6348 brz,pn %l6, 1f
62 stx %l6, [%g3 + TI_REG_WINDOW + 0x30]79 stw %l6, [%g3 + TI_REG_WINDOW + 0x18]
39 #define saved_g6 l6 /* Global save register T */263 clr %l6
1 …l6.09375 -8.65625l1.34375 0l0 8.65625l1.796875 0l0 1.5l-1.796875 0l0 3.203125l-1.640625 0zm0 -4.70…
16 jmpl %l4 + %lo(trap_setup), %l6;22 #define RESTORE_ALL b ret_trap_entry; clr %l6;
21 clr %l4; clr %l5; clr %l6; clr %l7; \258 stx %l6, [%sp + STACK_BIAS + 0x30]; \279 stx %l6, [%sp + STACK_BIAS + 0x30]; \309 stxa %l6, [%g1 + %g0] ASI; \337 stxa %l6, [%sp + STACK_BIAS + 0x30] %asi; \371 stx %l6, [%g3 + TI_REG_WINDOW + 0x30]; \405 stwa %l6, [%g1 + %g0] ASI; \436 stwa %l6, [%sp + 0x18] %asi; \470 stw %l6, [%g3 + TI_REG_WINDOW + 0x18]; \514 ldx [%sp + STACK_BIAS + 0x30], %l6; \[all …]
20 std %l6, [%reg + RW_L6]; \31 ldd [%reg + RW_L6], %l6; \
478 mov %i4, %l6481 ldda [%l6 + 0x00] %asi, %g2 /* %g2/%g3 = src3 + 0x00 */493 ldda [%l6 + 0x10] %asi, %g2 /* %g2/%g3 = src3 + 0x10 */506 ldda [%l6 + 0x20] %asi, %g2 /* %g2/%g3 = src3 + 0x20 */519 ldda [%l6 + 0x30] %asi, %g2 /* %g2/%g3 = src3 + 0x30 */524 prefetch [%l6 + 0x40], #one_read541 add %l6, 0x40, %l6562 mov %i4, %l6566 ldda [%l6 + 0x00] %asi, %g2 /* %g2/%g3 = src3 + 0x00 */577 ldda [%l6 + 0x10] %asi, %g2 /* %g2/%g3 = src3 + 0x10 */[all …]
78 vdd-l6-l9-supply = <&vreg_s8c_1p3>;230 vdd-l4-l5-l6-supply = <&vreg_bob>;336 vdd-l5-l6-supply = <&vreg_bob>;
73 vdd-l6-l9-supply = <&vreg_s8c_1p3>;225 vdd-l4-l5-l6-supply = <&vreg_bob>;331 vdd-l5-l6-supply = <&vreg_bob>;
86 vdd-l6-l9-supply = <&vreg_s8c_1p3>;217 vdd-l4-l5-l6-supply = <&vreg_bob>;321 vdd-l5-l6-supply = <&vreg_bob>;
63 vdd-l6-l9-l10-supply = <&vreg_s12b_1p25>;152 vdd-l6-l9-l11-supply = <&vreg_bob>;299 vdd-l5-l6-supply = <&vreg_s1c_1p86>;
82 vdd-l6-l9-supply = <&vreg_s8c_1p3>;234 vdd-l4-l5-l6-supply = <&vreg_bob>;340 vdd-l5-l6-supply = <&vreg_bob>;
235 pm6125_l6: l6 {362 pmr735a_l6: l6 {
67 vdd-l6-l9-l10-supply = <&vreg_s11b_0p95>;156 vdd-l6-l9-l11-supply = <&vreg_bob>;
181 vdd-l6-l9-supply = <&vreg_s8c_1p35>;311 vdd-l4-l5-l6-supply = <&vreg_bob>;417 vdd-l5-l6-supply = <&vreg_bob>;
298 #define fls16(l, l0, l1, l2, l3, l4, l5, l6, l7, r, t0, t1, t2, t3, tt0, \ argument326 vpxor l6, t2, l6; \327 vmovdqu l6, 6 * 16(l); \407 vpor l6, t2, t2; \
