Searched refs:global_ctrl (Results 1 – 10 of 10) sorted by relevance
302 u32 global_ctrl; in disable_hdm() local306 global_ctrl = readl(hdm + CXL_HDM_DECODER_CTRL_OFFSET); in disable_hdm()307 writel(global_ctrl & ~CXL_HDM_DECODER_ENABLE, in disable_hdm()314 u32 global_ctrl; in devm_cxl_enable_hdm() local316 global_ctrl = readl(hdm + CXL_HDM_DECODER_CTRL_OFFSET); in devm_cxl_enable_hdm()317 writel(global_ctrl | CXL_HDM_DECODER_ENABLE, in devm_cxl_enable_hdm()442 u32 global_ctrl = 0; in cxl_hdm_decode_init() local445 global_ctrl = readl(hdm + CXL_HDM_DECODER_CTRL_OFFSET); in cxl_hdm_decode_init()451 if (global_ctrl & CXL_HDM_DECODER_ENABLE || (!hdm && info->mem_enabled)) in cxl_hdm_decode_init()
570 msr_info->data = pmu->global_ctrl; in kvm_pmu_get_msr()616 if (pmu->global_ctrl != data) { in kvm_pmu_set_msr()617 diff = pmu->global_ctrl ^ data; in kvm_pmu_set_msr()618 pmu->global_ctrl = data; in kvm_pmu_set_msr()
253 return test_bit(pmc->idx, (unsigned long *)&pmu->global_ctrl); in pmc_is_globally_enabled()
290 uint64_t global_ctrl; member
248 pmu->global_ctrl = pmu->global_status = 0; in amd_pmu_reset()
653 pmu->fixed_ctr_ctrl = pmu->global_ctrl = pmu->global_status = 0; in intel_pmu_reset()773 for_each_set_bit(bit, (unsigned long *)&pmu->global_ctrl, in intel_pmu_cross_mapped_check()
7135 if (pmu->pebs_enable & pmu->global_ctrl) in atomic_switch_perf_msrs()
222 reg = &ctxt->global_ctrl; in xen_intel_pmu_emulate()
4063 int global_ctrl, pebs_enable; in intel_guest_get_msrs() local4066 global_ctrl = (*nr)++; in intel_guest_get_msrs()4067 arr[global_ctrl] = (struct perf_guest_switch_msr){ in intel_guest_get_msrs()4123 arr[global_ctrl].guest &= ~kvm_pmu->host_cross_mapped_mask; in intel_guest_get_msrs()4125 arr[global_ctrl].guest |= arr[pebs_enable].guest; in intel_guest_get_msrs()
522 u64 global_ctrl; member
