Searched refs:glitch (Results 1 – 11 of 11) sorted by relevance
150 struct catpt_notify_glitch glitch; in catpt_dsp_notify_stream() local168 memcpy_fromio(&glitch, catpt_inbox_addr(cdev), sizeof(glitch)); in catpt_dsp_notify_stream()169 trace_catpt_ipc_payload((u8 *)&glitch, sizeof(glitch)); in catpt_dsp_notify_stream()172 glitch.type, glitch.presentation_pos, in catpt_dsp_notify_stream()173 glitch.write_pos); in catpt_dsp_notify_stream()
382 bool glitch) in __nmk_gpio_set_mode_safe() argument387 if (glitch && nmk_chip->set_ioforce) { in __nmk_gpio_set_mode_safe()399 if (glitch && nmk_chip->set_ioforce) { in __nmk_gpio_set_mode_safe()1532 bool glitch; in nmk_pmx_set() local1564 glitch = ((g->altsetting & NMK_GPIO_ALT_C) == NMK_GPIO_ALT_C); in nmk_pmx_set()1566 if (glitch) { in nmk_pmx_set()1606 (g->altsetting & NMK_GPIO_ALT_C), glitch); in nmk_pmx_set()1626 if (glitch) { in nmk_pmx_set()
757 * VPU_0 and VPU_1 muxed to a single clock by a glitch759 * Same for VAPB but with a final gate after the glitch free mux.
827 * VPU_0 and VPU_1 muxed to a single clock by a glitch829 * Same for VAPB but with a final gate after the glitch free mux.
1242 * VPU_0 and VPU_1 muxed to a single clock by a glitch1244 * Same for VAPB but with a final gate after the glitch free mux.
1643 * VPU_0 and VPU_1 muxed to a single clock by a glitch1645 * Same for VAPB but with a final gate after the glitch free mux.
395 * back to one causes a power output glitch, so install a hog to keep
56 input de-glitch/debounce logic, sometimes with software controls.
40 input de-glitch/debounce logic, sometimes with software controls.275 setup of an output GPIO's value. This allows a glitch-free migration from a632 initializing the value as low. To ensure glitch free
77 initializing the value as low. To ensure glitch free
107 do not suffer from almost any glitch due to the background workload.
