Searched refs:gb_addr_config_fields (Results 1 – 7 of 7) sorted by relevance
217 adev->gfx.config.gb_addr_config_fields.num_pipes; in fill_gfx9_tiling_info_from_device()219 adev->gfx.config.gb_addr_config_fields.num_banks; in fill_gfx9_tiling_info_from_device()221 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size; in fill_gfx9_tiling_info_from_device()223 adev->gfx.config.gb_addr_config_fields.num_se; in fill_gfx9_tiling_info_from_device()225 adev->gfx.config.gb_addr_config_fields.max_compress_frags; in fill_gfx9_tiling_info_from_device()227 adev->gfx.config.gb_addr_config_fields.num_rb_per_se; in fill_gfx9_tiling_info_from_device()230 tiling_info->gfx9.num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs; in fill_gfx9_tiling_info_from_device()360 int pipe_xor_bits = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes); in add_gfx10_1_modifiers()405 int pipes = ilog2(adev->gfx.config.gb_addr_config_fields.num_pipes); in add_gfx9_modifiers()407 ilog2(adev->gfx.config.gb_addr_config_fields.num_se)); in add_gfx9_modifiers()[all …]
731 num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs; in convert_tiling_flags_to_modifier()732 num_pipes = adev->gfx.config.gb_addr_config_fields.num_pipes; in convert_tiling_flags_to_modifier()806 packers = ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs); in convert_tiling_flags_to_modifier()811 ilog2(adev->gfx.config.gb_addr_config_fields.num_pkrs)); in convert_tiling_flags_to_modifier()817 rb = ilog2(adev->gfx.config.gb_addr_config_fields.num_se) + in convert_tiling_flags_to_modifier()818 ilog2(adev->gfx.config.gb_addr_config_fields.num_rb_per_se); in convert_tiling_flags_to_modifier()820 ilog2(adev->gfx.config.gb_addr_config_fields.num_se)); in convert_tiling_flags_to_modifier()822 ilog2(adev->gfx.config.gb_addr_config_fields.num_banks)); in convert_tiling_flags_to_modifier()
220 struct gb_addr_config gb_addr_config_fields; member
701 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << in gfx_v9_4_3_gpu_early_init()708 adev->gfx.config.gb_addr_config_fields.num_pipes; in gfx_v9_4_3_gpu_early_init()710 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << in gfx_v9_4_3_gpu_early_init()715 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << in gfx_v9_4_3_gpu_early_init()720 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << in gfx_v9_4_3_gpu_early_init()725 adev->gfx.config.gb_addr_config_fields.num_se = 1 << in gfx_v9_4_3_gpu_early_init()730 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + in gfx_v9_4_3_gpu_early_init()
4213 adev->gfx.config.gb_addr_config_fields.num_pkrs = in get_gb_addr_config()4218 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << in get_gb_addr_config()4223 adev->gfx.config.gb_addr_config_fields.num_pipes; in get_gb_addr_config()4225 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << in get_gb_addr_config()4228 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << in get_gb_addr_config()4231 adev->gfx.config.gb_addr_config_fields.num_se = 1 << in get_gb_addr_config()4234 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + in get_gb_addr_config()
1927 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << in gfx_v9_0_gpu_early_init()1934 adev->gfx.config.gb_addr_config_fields.num_pipes; in gfx_v9_0_gpu_early_init()1936 adev->gfx.config.gb_addr_config_fields.num_banks = 1 << in gfx_v9_0_gpu_early_init()1941 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << in gfx_v9_0_gpu_early_init()1946 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << in gfx_v9_0_gpu_early_init()1951 adev->gfx.config.gb_addr_config_fields.num_se = 1 << in gfx_v9_0_gpu_early_init()1956 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + in gfx_v9_0_gpu_early_init()
4386 adev->gfx.config.gb_addr_config_fields.num_pkrs = in gfx_v10_0_gpu_early_init()4405 adev->gfx.config.gb_addr_config_fields.num_pipes = 1 << in gfx_v10_0_gpu_early_init()4410 adev->gfx.config.gb_addr_config_fields.num_pipes; in gfx_v10_0_gpu_early_init()4412 adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 << in gfx_v10_0_gpu_early_init()4415 adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 << in gfx_v10_0_gpu_early_init()4418 adev->gfx.config.gb_addr_config_fields.num_se = 1 << in gfx_v10_0_gpu_early_init()4421 adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 + in gfx_v10_0_gpu_early_init()
