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Searched refs:enable_bit (Results 1 – 25 of 58) sorted by relevance

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/Linux-v6.6/arch/arm/mach-omap1/
Dclock_data.c100 .enable_bit = EN_CKOUT_ARM,
110 .enable_bit = CONF_MOD_SOSSI_CLK_EN_R,
131 .enable_bit = EN_PERCK,
148 .enable_bit = EN_GPIOCK,
158 .enable_bit = EN_XORPCK,
170 .enable_bit = EN_TIMCK,
181 .enable_bit = EN_WDTCK,
201 .enable_bit = EN_DSPCK,
220 .enable_bit = EN_PERCK,
231 .enable_bit = EN_XORPCK,
[all …]
Dclock.c50 return val & 1 << clk->enable_bit ? 48000000 : 12000000; in omap1_uart_recalc()
198 ret = regval32 & (1 << clk->enable_bit); in omap1_clk_is_enabled()
388 val = 1 << clk->enable_bit; in omap1_set_uart_rate()
395 val |= __raw_readl(clk->enable_reg) & ~(1 << clk->enable_bit); in omap1_set_uart_rate()
554 regval32 |= (1 << clk->enable_bit); in omap1_clk_enable_generic()
558 regval16 |= (1 << clk->enable_bit); in omap1_clk_enable_generic()
599 regval32 &= ~(1 << clk->enable_bit); in omap1_clk_disable_generic()
603 regval16 &= ~(1 << clk->enable_bit); in omap1_clk_disable_generic()
/Linux-v6.6/tools/power/cpupower/utils/idle_monitor/
Damd_fam14h_idle.c98 unsigned int *enable_bit, in amd_fam14h_get_pci_info() argument
103 *enable_bit = PCI_NON_PC0_ENABLE_BIT; in amd_fam14h_get_pci_info()
107 *enable_bit = PCI_PC1_ENABLE_BIT; in amd_fam14h_get_pci_info()
111 *enable_bit = PCI_PC6_ENABLE_BIT; in amd_fam14h_get_pci_info()
115 *enable_bit = PCI_NBP1_ENTERED_BIT; in amd_fam14h_get_pci_info()
126 int enable_bit, pci_offset, ret; in amd_fam14h_init() local
129 ret = amd_fam14h_get_pci_info(state, &pci_offset, &enable_bit, cpu); in amd_fam14h_init()
136 val |= 1 << enable_bit; in amd_fam14h_init()
145 val |= 1 << enable_bit; in amd_fam14h_init()
149 state->name, PCI_MONITOR_ENABLE_REG, enable_bit, in amd_fam14h_init()
[all …]
/Linux-v6.6/drivers/clk/ti/
Dclkt_dflt.c146 *other_bit = clk->enable_bit; in omap2_clk_dflt_find_companion()
172 *idlest_bit = clk->enable_bit; in omap2_clk_dflt_find_idlest()
222 v &= ~(1 << clk->enable_bit); in omap2_dflt_clk_enable()
224 v |= (1 << clk->enable_bit); in omap2_dflt_clk_enable()
252 v |= (1 << clk->enable_bit); in omap2_dflt_clk_disable()
254 v &= ~(1 << clk->enable_bit); in omap2_dflt_clk_disable()
279 v ^= BIT(clk->enable_bit); in omap2_dflt_clk_is_enabled()
281 v &= BIT(clk->enable_bit); in omap2_dflt_clk_is_enabled()
Dinterface.c44 clk_hw->enable_bit = bit_idx; in _register_interface()
67 u8 enable_bit = 0; in _of_ti_interface_clk_setup() local
75 enable_bit = val; in _of_ti_interface_clk_setup()
85 enable_bit, ops); in _of_ti_interface_clk_setup()
Dclkt_iclk.c37 v |= (1 << clk->enable_bit); in omap2_clkt_iclk_allow_idle()
52 v &= ~(1 << clk->enable_bit); in omap2_clkt_iclk_deny_idle()
75 *idlest_bit = clk->enable_bit; in omap2430_clk_i2chs_find_idlest()
Dgate.c108 clk_hw->enable_bit = bit_idx; in _register_gate()
134 u8 enable_bit = 0; in _of_ti_gate_clk_setup() local
144 enable_bit = val; in _of_ti_gate_clk_setup()
162 enable_bit, clk_gate_flags, ops, hw_ops); in _of_ti_gate_clk_setup()
184 gate->enable_bit = val; in _of_ti_composite_gate_clk_setup()
Dclk-3xxx.c153 *idlest_bit = clk->enable_bit + AM35XX_IPSS_ICK_EN_ACK_OFFSET; in am35xx_clk_find_idlest()
176 if (clk->enable_bit & AM35XX_IPSS_ICK_MASK) in am35xx_clk_find_companion()
177 *other_bit = clk->enable_bit + AM35XX_IPSS_ICK_FCK_OFFSET; in am35xx_clk_find_companion()
179 *other_bit = clk->enable_bit - AM35XX_IPSS_ICK_FCK_OFFSET; in am35xx_clk_find_companion()
Dclkctrl.c148 if (!clk->enable_bit) in _omap4_clkctrl_clk_enable()
154 val |= clk->enable_bit; in _omap4_clkctrl_clk_enable()
178 if (!clk->enable_bit) in _omap4_clkctrl_clk_disable()
211 if (val & clk->enable_bit) in _omap4_clkctrl_clk_is_enabled()
344 clk_hw->enable_bit = data->bit; in _ti_clkctrl_setup_gate()
663 hw->enable_bit = MODULEMODE_SWCTRL; in _ti_omap4_clkctrl_setup()
665 hw->enable_bit = MODULEMODE_HWCTRL; in _ti_omap4_clkctrl_setup()
/Linux-v6.6/drivers/clk/
Dclk-max9485.c73 u8 enable_bit; member
115 clk_hw->enable_bit, in max9485_clk_prepare()
116 clk_hw->enable_bit); in max9485_clk_prepare()
123 max9485_update_bits(clk_hw->drvdata, clk_hw->enable_bit, 0); in max9485_clk_unprepare()
206 u8 enable_bit; member
213 .enable_bit = MAX9485_MCLK_ENABLE,
231 .enable_bit = MAX9485_CLKOUT1_ENABLE,
240 .enable_bit = MAX9485_CLKOUT2_ENABLE,
321 drvdata->hw[i].enable_bit = max9485_clks[i].enable_bit; in max9485_i2c_probe()
/Linux-v6.6/tools/testing/selftests/user_events/
Dftrace_test.c178 reg.enable_bit = 31; in check_print_fmt()
243 reg.enable_bit = 31; in TEST_F()
260 reg.enable_bit = 30; in TEST_F()
265 reg.enable_bit = 29; in TEST_F()
277 ASSERT_EQ(1 << reg.enable_bit, self->check); in TEST_F()
306 reg.enable_bit = 31; in TEST_F()
342 ASSERT_NE(1 << reg.enable_bit, self->check); in TEST_F()
363 reg.enable_bit = 31; in TEST_F()
380 ASSERT_EQ(1 << reg.enable_bit, self->check); in TEST_F()
397 reg.enable_bit = 31; in TEST_F()
[all …]
Dperf_test.c144 reg.enable_bit = 31; in TEST_F()
174 ASSERT_EQ(1 << reg.enable_bit, self->check); in TEST_F()
208 reg.enable_bit = 31; in TEST_F()
236 ASSERT_EQ(1 << reg.enable_bit, self->check); in TEST_F()
/Linux-v6.6/drivers/clk/renesas/
Dclk-sh73a0.c91 u32 enable_bit = name[3] - '0'; in sh73a0_cpg_register_clock() local
94 switch (enable_bit) { in sh73a0_cpg_register_clock()
110 if (readl(base + CPG_PLLECR) & BIT(enable_bit)) { in sh73a0_cpg_register_clock()
113 if (enable_bit == 1 || enable_bit == 2) in sh73a0_cpg_register_clock()
/Linux-v6.6/drivers/regulator/
Dtps6586x-regulator.c59 int enable_bit[2]; member
128 .enable_bit[0] = (ebit0), \
130 .enable_bit[1] = (ebit1),
153 .enable_bit[0] = (ebit0), \
155 .enable_bit[1] = (ebit1),
274 ri->enable_bit[0] == ri->enable_bit[1]) in tps6586x_regulator_preinit()
285 if (!(val2 & (1 << ri->enable_bit[1]))) in tps6586x_regulator_preinit()
292 if (!(val1 & (1 << ri->enable_bit[0]))) { in tps6586x_regulator_preinit()
294 1 << ri->enable_bit[0]); in tps6586x_regulator_preinit()
300 1 << ri->enable_bit[1]); in tps6586x_regulator_preinit()
Dmc13xxx.h16 int enable_bit; member
67 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
85 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
100 .enable_bit = prefix ## _reg ## _ ## _name ## EN, \
Dmc13xxx-regulator-core.c36 mc13xxx_regulators[id].enable_bit, in mc13xxx_regulator_enable()
37 mc13xxx_regulators[id].enable_bit); in mc13xxx_regulator_enable()
49 mc13xxx_regulators[id].enable_bit, 0); in mc13xxx_regulator_disable()
63 return (val & mc13xxx_regulators[id].enable_bit) != 0; in mc13xxx_regulator_is_enabled()
Dmc13783-regulator.c330 u32 en_val = mc13xxx_regulators[id].enable_bit; in mc13783_gpo_regulator_enable()
339 return mc13783_powermisc_rmw(priv, mc13xxx_regulators[id].enable_bit, in mc13783_gpo_regulator_enable()
355 dis_val = mc13xxx_regulators[id].enable_bit; in mc13783_gpo_regulator_disable()
357 return mc13783_powermisc_rmw(priv, mc13xxx_regulators[id].enable_bit, in mc13783_gpo_regulator_disable()
380 return (val & mc13xxx_regulators[id].enable_bit) != 0; in mc13783_gpo_regulator_is_enabled()
Dda903x-regulator.c82 int enable_bit; member
141 1 << info->enable_bit); in da903x_enable()
150 1 << info->enable_bit); in da903x_disable()
164 return !!(reg_val & (1 << info->enable_bit)); in da903x_is_enabled()
326 .enable_bit = (ebit), \
348 .enable_bit = (ebit), \
Dmc13892-regulator.c337 u32 en_val = mc13892_regulators[id].enable_bit; in mc13892_gpo_regulator_enable()
338 u32 mask = mc13892_regulators[id].enable_bit; in mc13892_gpo_regulator_enable()
362 dis_val = mc13892_regulators[id].enable_bit; in mc13892_gpo_regulator_disable()
364 return mc13892_powermisc_rmw(priv, mc13892_regulators[id].enable_bit, in mc13892_gpo_regulator_disable()
386 return (val & mc13892_regulators[id].enable_bit) != 0; in mc13892_gpo_regulator_is_enabled()
/Linux-v6.6/include/linux/
Dsh_clk.h57 unsigned int enable_bit; member
121 .enable_bit = _enable_bit, \
155 .enable_bit = _shift, \
179 .enable_bit = 0, /* unused */ \
192 .enable_bit = 0, /* unused */ \
/Linux-v6.6/drivers/sh/clk/
Dcpg.c41 sh_clk_write(sh_clk_read(clk) & ~(1 << clk->enable_bit), clk); in sh_clk_mstp_enable()
56 (read(mapped_status) & (1 << clk->enable_bit)) && i; in sh_clk_mstp_enable()
61 clk->enable_reg, clk->enable_bit); in sh_clk_mstp_enable()
70 sh_clk_write(sh_clk_read(clk) | (1 << clk->enable_bit), clk); in sh_clk_mstp_disable()
123 idx = (sh_clk_read(clk) >> clk->enable_bit) & clk->div_mask; in sh_clk_div_recalc()
139 value &= ~(clk->div_mask << clk->enable_bit); in sh_clk_div_set_rate()
140 value |= (idx << clk->enable_bit); in sh_clk_div_set_rate()
/Linux-v6.6/drivers/xen/xen-pciback/
Dconf_space_capability.c193 u16 enable_bit; /* bit for enabling MSI/MSI-X */ member
197 .enable_bit = PCI_MSI_FLAGS_ENABLE,
201 .enable_bit = PCI_MSIX_FLAGS_ENABLE,
238 if (new_value & field_config->enable_bit) { in msi_msix_flags_write()
/Linux-v6.6/drivers/clk/ingenic/
Dx1830-cgu.c130 .enable_bit = 0,
153 .enable_bit = 0,
176 .enable_bit = 0,
199 .enable_bit = 0,
Dcgu.c239 if (pll_info->enable_bit >= 0 && (ctl & BIT(pll_info->enable_bit))) in ingenic_pll_set_rate()
257 if (pll_info->enable_bit < 0) in ingenic_pll_enable()
271 ctl |= BIT(pll_info->enable_bit); in ingenic_pll_enable()
290 if (pll_info->enable_bit < 0) in ingenic_pll_disable()
296 ctl &= ~BIT(pll_info->enable_bit); in ingenic_pll_disable()
310 if (pll_info->enable_bit < 0) in ingenic_pll_is_enabled()
315 return !!(ctl & BIT(pll_info->enable_bit)); in ingenic_pll_is_enabled()
/Linux-v6.6/drivers/watchdog/
DiTCO_wdt.c152 u32 enable_bit; in no_reboot_bit() local
157 enable_bit = 0x00000010; in no_reboot_bit()
160 enable_bit = 0x00000020; in no_reboot_bit()
165 enable_bit = 0x00000002; in no_reboot_bit()
169 return enable_bit; in no_reboot_bit()

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