Searched refs:dsi_phy_write_udelay (Results 1 – 3 of 3) sorted by relevance
/Linux-v6.6/drivers/gpu/drm/msm/dsi/phy/ |
D | dsi_phy_28nm.c | 107 dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_TEST_CFG, in pll_28nm_software_reset() 109 dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_TEST_CFG, 0x00, 1); in pll_28nm_software_reset() 306 dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 1); in _dsi_pll_28nm_vco_prepare_hpm() 309 dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200); in _dsi_pll_28nm_vco_prepare_hpm() 312 dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 500); in _dsi_pll_28nm_vco_prepare_hpm() 315 dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600); in _dsi_pll_28nm_vco_prepare_hpm() 319 dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, in _dsi_pll_28nm_vco_prepare_hpm() 336 dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 1); in _dsi_pll_28nm_vco_prepare_hpm() 339 dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200); in _dsi_pll_28nm_vco_prepare_hpm() 342 dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 250); in _dsi_pll_28nm_vco_prepare_hpm() [all …]
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D | dsi_phy.h | 17 #define dsi_phy_write_udelay(offset, data, delay_us) { msm_writel((data), (offset)); udelay(delay_u… macro
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D | dsi_phy_14nm.c | 375 dsi_phy_write_udelay(cmn_base + REG_DSI_14nm_PHY_CMN_CTRL_1, 0x20, 10); in pll_14nm_software_reset()
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