Searched refs:drvsel (Results 1 – 3 of 3) sorted by relevance
23 #define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel) \ argument24 ((((smplsel) & 0x7) << 3) | (((drvsel) & 0x7) << 0))26 #define SYSMGR_SDMMC_CTRL_SET_AS10(smplsel, drvsel) \ argument27 ((((smplsel) & 0x7) << 4) | (((drvsel) & 0x7) << 0))
27 #define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel, reg_shift) \ argument28 ((((smplsel) & 0x7) << reg_shift) | (((drvsel) & 0x7) << 0))
28 value is the cclk_in_drv(drvsel). The clk-phase is used to enable the correct
