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Searched refs:dpcd_lane_status_updated (Results 1 – 6 of 6) sorted by relevance

/Linux-v6.6/drivers/gpu/drm/amd/display/dc/link/protocols/
Dlink_dp_training_128b_132b.c79 union lane_align_status_updated dpcd_lane_status_updated = {0}; in dp_perform_128b_132b_channel_eq_done_sequence() local
94 &dpcd_lane_status_updated, dpcd_lane_adjust, DPRX); in dp_perform_128b_132b_channel_eq_done_sequence()
112 &dpcd_lane_status_updated, dpcd_lane_adjust, DPRX); in dp_perform_128b_132b_channel_eq_done_sequence()
124 } else if (dpcd_lane_status_updated.bits.LT_FAILED_128b_132b) { in dp_perform_128b_132b_channel_eq_done_sequence()
137 } else if (dpcd_lane_status_updated.bits.EQ_INTERLANE_ALIGN_DONE_128b_132b) { in dp_perform_128b_132b_channel_eq_done_sequence()
142 } else if (dpcd_lane_status_updated.bits.LT_FAILED_128b_132b) { in dp_perform_128b_132b_channel_eq_done_sequence()
149 &dpcd_lane_status_updated, dpcd_lane_adjust, DPRX); in dp_perform_128b_132b_channel_eq_done_sequence()
164 union lane_align_status_updated dpcd_lane_status_updated = {0}; in dp_perform_128b_132b_cds_done_sequence() local
178 &dpcd_lane_status_updated, dpcd_lane_adjust, DPRX); in dp_perform_128b_132b_cds_done_sequence()
182 dpcd_lane_status_updated.bits.CDS_INTERLANE_ALIGN_DONE_128b_132b) { in dp_perform_128b_132b_cds_done_sequence()
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Dlink_dp_training_fixed_vs_pe_retimer.c319 union lane_align_status_updated dpcd_lane_status_updated; in dp_perform_fixed_vs_pe_training_sequence_legacy() local
327 memset(&dpcd_lane_status_updated, '\0', in dp_perform_fixed_vs_pe_training_sequence_legacy()
328 sizeof(dpcd_lane_status_updated)); in dp_perform_fixed_vs_pe_training_sequence_legacy()
401 &dpcd_lane_status_updated, in dp_perform_fixed_vs_pe_training_sequence_legacy()
448 union lane_align_status_updated dpcd_lane_status_updated = {0}; in dp_perform_fixed_vs_pe_training_sequence_legacy() local
507 &dpcd_lane_status_updated, in dp_perform_fixed_vs_pe_training_sequence_legacy()
520 dp_is_interlane_aligned(dpcd_lane_status_updated)) { in dp_perform_fixed_vs_pe_training_sequence_legacy()
665 union lane_align_status_updated dpcd_lane_status_updated; in dp_perform_fixed_vs_pe_training_sequence() local
673 memset(&dpcd_lane_status_updated, '\0', in dp_perform_fixed_vs_pe_training_sequence()
674 sizeof(dpcd_lane_status_updated)); in dp_perform_fixed_vs_pe_training_sequence()
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Dlink_dp_training_8b_10b.c165 union lane_align_status_updated dpcd_lane_status_updated; in perform_8b_10b_clock_recovery_sequence() local
172 memset(&dpcd_lane_status_updated, '\0', in perform_8b_10b_clock_recovery_sequence()
173 sizeof(dpcd_lane_status_updated)); in perform_8b_10b_clock_recovery_sequence()
223 &dpcd_lane_status_updated, in perform_8b_10b_clock_recovery_sequence()
280 union lane_align_status_updated dpcd_lane_status_updated = {0}; in perform_8b_10b_channel_equalization_sequence() local
329 &dpcd_lane_status_updated, in perform_8b_10b_channel_equalization_sequence()
342 dp_is_interlane_aligned(dpcd_lane_status_updated)) in perform_8b_10b_channel_equalization_sequence()
Dlink_dp_training_dpia.c300 union lane_align_status_updated dpcd_lane_status_updated = {0}; in dpia_training_cr_non_transparent() local
394 &dpcd_lane_status_updated, in dpia_training_cr_non_transparent()
470 union lane_align_status_updated dpcd_lane_status_updated = {0}; in dpia_training_cr_transparent() local
502 &dpcd_lane_status_updated, in dpia_training_cr_transparent()
624 union lane_align_status_updated dpcd_lane_status_updated = {0}; in dpia_training_eq_non_transparent() local
708 &dpcd_lane_status_updated, in dpia_training_eq_non_transparent()
724 dp_is_interlane_aligned(dpcd_lane_status_updated)) { in dpia_training_eq_non_transparent()
772 union lane_align_status_updated dpcd_lane_status_updated = {0}; in dpia_training_eq_transparent() local
795 &dpcd_lane_status_updated, in dpia_training_eq_transparent()
814 if (dp_is_interlane_aligned(dpcd_lane_status_updated) || (link->is_automated && retries_eq)) { in dpia_training_eq_transparent()
Dlink_dp_irq_handler.c276 union lane_align_status_updated dpcd_lane_status_updated; in read_dpcd204h_on_irq_hpd() local
281 &dpcd_lane_status_updated.raw, in read_dpcd204h_on_irq_hpd()
286 dpcd_lane_status_updated.bits.EQ_INTERLANE_ALIGN_DONE_128b_132b; in read_dpcd204h_on_irq_hpd()
288 dpcd_lane_status_updated.bits.CDS_INTERLANE_ALIGN_DONE_128b_132b; in read_dpcd204h_on_irq_hpd()
Dlink_dp_training.c1353 union lane_align_status_updated dpcd_lane_status_updated = {0}; in perform_post_lt_adj_req_sequence() local
1370 &dpcd_lane_status_updated, in perform_post_lt_adj_req_sequence()
1374 if (dpcd_lane_status_updated.bits. in perform_post_lt_adj_req_sequence()
1383 !dp_is_interlane_aligned(dpcd_lane_status_updated)) in perform_post_lt_adj_req_sequence()