1 /*
2 * Copyright 2019 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #ifndef DMUB_CMD_H
27 #define DMUB_CMD_H
28
29 #if defined(_TEST_HARNESS) || defined(FPGA_USB4)
30 #include "dmub_fw_types.h"
31 #include "include_legacy/atomfirmware.h"
32
33 #if defined(_TEST_HARNESS)
34 #include <string.h>
35 #endif
36 #else
37
38 #include <asm/byteorder.h>
39 #include <linux/types.h>
40 #include <linux/string.h>
41 #include <linux/delay.h>
42
43 #include "atomfirmware.h"
44
45 #endif // defined(_TEST_HARNESS) || defined(FPGA_USB4)
46
47 //<DMUB_TYPES>==================================================================
48 /* Basic type definitions. */
49
50 #define __forceinline inline
51
52 /**
53 * Flag from driver to indicate that ABM should be disabled gradually
54 * by slowly reversing all backlight programming and pixel compensation.
55 */
56 #define SET_ABM_PIPE_GRADUALLY_DISABLE 0
57
58 /**
59 * Flag from driver to indicate that ABM should be disabled immediately
60 * and undo all backlight programming and pixel compensation.
61 */
62 #define SET_ABM_PIPE_IMMEDIATELY_DISABLE 255
63
64 /**
65 * Flag from driver to indicate that ABM should be disabled immediately
66 * and keep the current backlight programming and pixel compensation.
67 */
68 #define SET_ABM_PIPE_IMMEDIATE_KEEP_GAIN_DISABLE 254
69
70 /**
71 * Flag from driver to set the current ABM pipe index or ABM operating level.
72 */
73 #define SET_ABM_PIPE_NORMAL 1
74
75 /**
76 * Number of ambient light levels in ABM algorithm.
77 */
78 #define NUM_AMBI_LEVEL 5
79
80 /**
81 * Number of operating/aggression levels in ABM algorithm.
82 */
83 #define NUM_AGGR_LEVEL 4
84
85 /**
86 * Number of segments in the gamma curve.
87 */
88 #define NUM_POWER_FN_SEGS 8
89
90 /**
91 * Number of segments in the backlight curve.
92 */
93 #define NUM_BL_CURVE_SEGS 16
94
95 /* Maximum number of SubVP streams */
96 #define DMUB_MAX_SUBVP_STREAMS 2
97
98 /* Define max FPO streams as 4 for now. Current implementation today
99 * only supports 1, but could be more in the future. Reduce array
100 * size to ensure the command size remains less than 64 bytes if
101 * adding new fields.
102 */
103 #define DMUB_MAX_FPO_STREAMS 4
104
105 /* Maximum number of streams on any ASIC. */
106 #define DMUB_MAX_STREAMS 6
107
108 /* Maximum number of planes on any ASIC. */
109 #define DMUB_MAX_PLANES 6
110
111 /* Trace buffer offset for entry */
112 #define TRACE_BUFFER_ENTRY_OFFSET 16
113
114 /**
115 * Maximum number of dirty rects supported by FW.
116 */
117 #define DMUB_MAX_DIRTY_RECTS 3
118
119 /**
120 *
121 * PSR control version legacy
122 */
123 #define DMUB_CMD_PSR_CONTROL_VERSION_UNKNOWN 0x0
124 /**
125 * PSR control version with multi edp support
126 */
127 #define DMUB_CMD_PSR_CONTROL_VERSION_1 0x1
128
129
130 /**
131 * ABM control version legacy
132 */
133 #define DMUB_CMD_ABM_CONTROL_VERSION_UNKNOWN 0x0
134
135 /**
136 * ABM control version with multi edp support
137 */
138 #define DMUB_CMD_ABM_CONTROL_VERSION_1 0x1
139
140 /**
141 * Physical framebuffer address location, 64-bit.
142 */
143 #ifndef PHYSICAL_ADDRESS_LOC
144 #define PHYSICAL_ADDRESS_LOC union large_integer
145 #endif
146
147 /**
148 * OS/FW agnostic memcpy
149 */
150 #ifndef dmub_memcpy
151 #define dmub_memcpy(dest, source, bytes) memcpy((dest), (source), (bytes))
152 #endif
153
154 /**
155 * OS/FW agnostic memset
156 */
157 #ifndef dmub_memset
158 #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes))
159 #endif
160
161 #if defined(__cplusplus)
162 extern "C" {
163 #endif
164
165 /**
166 * OS/FW agnostic udelay
167 */
168 #ifndef dmub_udelay
169 #define dmub_udelay(microseconds) udelay(microseconds)
170 #endif
171
172 #pragma pack(push, 1)
173 #define ABM_NUM_OF_ACE_SEGMENTS 5
174
175 union abm_flags {
176 struct {
177 /**
178 * @abm_enabled: Indicates if ABM is enabled.
179 */
180 unsigned int abm_enabled : 1;
181
182 /**
183 * @disable_abm_requested: Indicates if driver has requested ABM to be disabled.
184 */
185 unsigned int disable_abm_requested : 1;
186
187 /**
188 * @disable_abm_immediately: Indicates if driver has requested ABM to be disabled
189 * immediately.
190 */
191 unsigned int disable_abm_immediately : 1;
192
193 /**
194 * @disable_abm_immediate_keep_gain: Indicates if driver has requested ABM
195 * to be disabled immediately and keep gain.
196 */
197 unsigned int disable_abm_immediate_keep_gain : 1;
198
199 /**
200 * @fractional_pwm: Indicates if fractional duty cycle for backlight PWM is enabled.
201 */
202 unsigned int fractional_pwm : 1;
203
204 /**
205 * @abm_gradual_bl_change: Indicates if algorithm has completed gradual adjustment
206 * of user backlight level.
207 */
208 unsigned int abm_gradual_bl_change : 1;
209 } bitfields;
210
211 unsigned int u32All;
212 };
213
214 struct abm_save_restore {
215 /**
216 * @flags: Misc. ABM flags.
217 */
218 union abm_flags flags;
219
220 /**
221 * @pause: true: pause ABM and get state
222 * false: unpause ABM after setting state
223 */
224 uint32_t pause;
225
226 /**
227 * @next_ace_slope: Next ACE slopes to be programmed in HW (u3.13)
228 */
229 uint32_t next_ace_slope[ABM_NUM_OF_ACE_SEGMENTS];
230
231 /**
232 * @next_ace_thresh: Next ACE thresholds to be programmed in HW (u10.6)
233 */
234 uint32_t next_ace_thresh[ABM_NUM_OF_ACE_SEGMENTS];
235
236 /**
237 * @next_ace_offset: Next ACE offsets to be programmed in HW (u10.6)
238 */
239 uint32_t next_ace_offset[ABM_NUM_OF_ACE_SEGMENTS];
240
241
242 /**
243 * @knee_threshold: Current x-position of ACE knee (u0.16).
244 */
245 uint32_t knee_threshold;
246 /**
247 * @current_gain: Current backlight reduction (u16.16).
248 */
249 uint32_t current_gain;
250 /**
251 * @curr_bl_level: Current actual backlight level converging to target backlight level.
252 */
253 uint16_t curr_bl_level;
254
255 /**
256 * @curr_user_bl_level: Current nominal backlight level converging to level requested by user.
257 */
258 uint16_t curr_user_bl_level;
259
260 };
261
262 /**
263 * union dmub_addr - DMUB physical/virtual 64-bit address.
264 */
265 union dmub_addr {
266 struct {
267 uint32_t low_part; /**< Lower 32 bits */
268 uint32_t high_part; /**< Upper 32 bits */
269 } u; /*<< Low/high bit access */
270 uint64_t quad_part; /*<< 64 bit address */
271 };
272 #pragma pack(pop)
273
274 /**
275 * Dirty rect definition.
276 */
277 struct dmub_rect {
278 /**
279 * Dirty rect x offset.
280 */
281 uint32_t x;
282
283 /**
284 * Dirty rect y offset.
285 */
286 uint32_t y;
287
288 /**
289 * Dirty rect width.
290 */
291 uint32_t width;
292
293 /**
294 * Dirty rect height.
295 */
296 uint32_t height;
297 };
298
299 /**
300 * Flags that can be set by driver to change some PSR behaviour.
301 */
302 union dmub_psr_debug_flags {
303 /**
304 * Debug flags.
305 */
306 struct {
307 /**
308 * Enable visual confirm in FW.
309 */
310 uint32_t visual_confirm : 1;
311
312 /**
313 * Force all selective updates to bw full frame updates.
314 */
315 uint32_t force_full_frame_update : 1;
316
317 /**
318 * Use HW Lock Mgr object to do HW locking in FW.
319 */
320 uint32_t use_hw_lock_mgr : 1;
321
322 /**
323 * Use TPS3 signal when restore main link.
324 */
325 uint32_t force_wakeup_by_tps3 : 1;
326
327 /**
328 * Back to back flip, therefore cannot power down PHY
329 */
330 uint32_t back_to_back_flip : 1;
331
332 } bitfields;
333
334 /**
335 * Union for debug flags.
336 */
337 uint32_t u32All;
338 };
339
340 /**
341 * Flags that can be set by driver to change some Replay behaviour.
342 */
343 union replay_debug_flags {
344 struct {
345 /**
346 * Enable visual confirm in FW.
347 */
348 uint32_t visual_confirm : 1;
349
350 /**
351 * @skip_crc: Set if need to skip CRC.
352 */
353 uint32_t skip_crc : 1;
354
355 /**
356 * @force_link_power_on: Force disable ALPM control
357 */
358 uint32_t force_link_power_on : 1;
359
360 /**
361 * @force_phy_power_on: Force phy power on
362 */
363 uint32_t force_phy_power_on : 1;
364
365 /**
366 * @timing_resync_disabled: Disabled Replay normal sleep mode timing resync
367 */
368 uint32_t timing_resync_disabled : 1;
369
370 /**
371 * @skip_crtc_disabled: CRTC disable skipped
372 */
373 uint32_t skip_crtc_disabled : 1;
374
375 /**
376 * @force_defer_one_frame_update: Force defer one frame update in ultra sleep mode
377 */
378 uint32_t force_defer_one_frame_update : 1;
379 /**
380 * @disable_delay_alpm_on: Force disable delay alpm on
381 */
382 uint32_t disable_delay_alpm_on : 1;
383 /**
384 * @disable_desync_error_check: Force disable desync error check
385 */
386 uint32_t disable_desync_error_check : 1;
387 /**
388 * @disable_desync_error_check: Force disable desync error check
389 */
390 uint32_t disable_dmub_save_restore : 1;
391
392 uint32_t reserved : 22;
393 } bitfields;
394
395 uint32_t u32All;
396 };
397
398 union replay_hw_flags {
399 struct {
400 /**
401 * @allow_alpm_fw_standby_mode: To indicate whether the
402 * ALPM FW standby mode is allowed
403 */
404 uint32_t allow_alpm_fw_standby_mode : 1;
405
406 /*
407 * @dsc_enable_status: DSC enable status in driver
408 */
409 uint32_t dsc_enable_status : 1;
410
411 /**
412 * @fec_enable_status: receive fec enable/disable status from driver
413 */
414 uint32_t fec_enable_status : 1;
415
416 /*
417 * @smu_optimizations_en: SMU power optimization.
418 * Only when active display is Replay capable and display enters Replay.
419 * Trigger interrupt to SMU to powerup/down.
420 */
421 uint32_t smu_optimizations_en : 1;
422
423 /**
424 * @otg_powered_down: Flag to keep track of OTG power state.
425 */
426 uint32_t otg_powered_down : 1;
427
428 /**
429 * @phy_power_state: Indicates current phy power state
430 */
431 uint32_t phy_power_state : 1;
432
433 /**
434 * @link_power_state: Indicates current link power state
435 */
436 uint32_t link_power_state : 1;
437 /**
438 * Use TPS3 signal when restore main link.
439 */
440 uint32_t force_wakeup_by_tps3 : 1;
441 } bitfields;
442
443 uint32_t u32All;
444 };
445
446 /**
447 * DMUB visual confirm color
448 */
449 struct dmub_feature_caps {
450 /**
451 * Max PSR version supported by FW.
452 */
453 uint8_t psr;
454 uint8_t fw_assisted_mclk_switch;
455 uint8_t reserved[4];
456 uint8_t subvp_psr_support;
457 uint8_t gecc_enable;
458 };
459
460 struct dmub_visual_confirm_color {
461 /**
462 * Maximum 10 bits color value
463 */
464 uint16_t color_r_cr;
465 uint16_t color_g_y;
466 uint16_t color_b_cb;
467 uint16_t panel_inst;
468 };
469
470 #if defined(__cplusplus)
471 }
472 #endif
473
474 //==============================================================================
475 //</DMUB_TYPES>=================================================================
476 //==============================================================================
477 //< DMUB_META>==================================================================
478 //==============================================================================
479 #pragma pack(push, 1)
480
481 /* Magic value for identifying dmub_fw_meta_info */
482 #define DMUB_FW_META_MAGIC 0x444D5542
483
484 /* Offset from the end of the file to the dmub_fw_meta_info */
485 #define DMUB_FW_META_OFFSET 0x24
486
487 /**
488 * struct dmub_fw_meta_info - metadata associated with fw binary
489 *
490 * NOTE: This should be considered a stable API. Fields should
491 * not be repurposed or reordered. New fields should be
492 * added instead to extend the structure.
493 *
494 * @magic_value: magic value identifying DMUB firmware meta info
495 * @fw_region_size: size of the firmware state region
496 * @trace_buffer_size: size of the tracebuffer region
497 * @fw_version: the firmware version information
498 * @dal_fw: 1 if the firmware is DAL
499 */
500 struct dmub_fw_meta_info {
501 uint32_t magic_value; /**< magic value identifying DMUB firmware meta info */
502 uint32_t fw_region_size; /**< size of the firmware state region */
503 uint32_t trace_buffer_size; /**< size of the tracebuffer region */
504 uint32_t fw_version; /**< the firmware version information */
505 uint8_t dal_fw; /**< 1 if the firmware is DAL */
506 uint8_t reserved[3]; /**< padding bits */
507 };
508
509 /**
510 * union dmub_fw_meta - ensures that dmub_fw_meta_info remains 64 bytes
511 */
512 union dmub_fw_meta {
513 struct dmub_fw_meta_info info; /**< metadata info */
514 uint8_t reserved[64]; /**< padding bits */
515 };
516
517 #pragma pack(pop)
518
519 //==============================================================================
520 //< DMUB Trace Buffer>================================================================
521 //==============================================================================
522 /**
523 * dmub_trace_code_t - firmware trace code, 32-bits
524 */
525 typedef uint32_t dmub_trace_code_t;
526
527 /**
528 * struct dmcub_trace_buf_entry - Firmware trace entry
529 */
530 struct dmcub_trace_buf_entry {
531 dmub_trace_code_t trace_code; /**< trace code for the event */
532 uint32_t tick_count; /**< the tick count at time of trace */
533 uint32_t param0; /**< trace defined parameter 0 */
534 uint32_t param1; /**< trace defined parameter 1 */
535 };
536
537 //==============================================================================
538 //< DMUB_STATUS>================================================================
539 //==============================================================================
540
541 /**
542 * DMCUB scratch registers can be used to determine firmware status.
543 * Current scratch register usage is as follows:
544 *
545 * SCRATCH0: FW Boot Status register
546 * SCRATCH5: LVTMA Status Register
547 * SCRATCH15: FW Boot Options register
548 */
549
550 /**
551 * union dmub_fw_boot_status - Status bit definitions for SCRATCH0.
552 */
553 union dmub_fw_boot_status {
554 struct {
555 uint32_t dal_fw : 1; /**< 1 if DAL FW */
556 uint32_t mailbox_rdy : 1; /**< 1 if mailbox ready */
557 uint32_t optimized_init_done : 1; /**< 1 if optimized init done */
558 uint32_t restore_required : 1; /**< 1 if driver should call restore */
559 uint32_t defer_load : 1; /**< 1 if VBIOS data is deferred programmed */
560 uint32_t fams_enabled : 1; /**< 1 if VBIOS data is deferred programmed */
561 uint32_t detection_required: 1; /**< if detection need to be triggered by driver */
562 uint32_t hw_power_init_done: 1; /**< 1 if hw power init is completed */
563 } bits; /**< status bits */
564 uint32_t all; /**< 32-bit access to status bits */
565 };
566
567 /**
568 * enum dmub_fw_boot_status_bit - Enum bit definitions for SCRATCH0.
569 */
570 enum dmub_fw_boot_status_bit {
571 DMUB_FW_BOOT_STATUS_BIT_DAL_FIRMWARE = (1 << 0), /**< 1 if DAL FW */
572 DMUB_FW_BOOT_STATUS_BIT_MAILBOX_READY = (1 << 1), /**< 1 if mailbox ready */
573 DMUB_FW_BOOT_STATUS_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if init done */
574 DMUB_FW_BOOT_STATUS_BIT_RESTORE_REQUIRED = (1 << 3), /**< 1 if driver should call restore */
575 DMUB_FW_BOOT_STATUS_BIT_DEFERRED_LOADED = (1 << 4), /**< 1 if VBIOS data is deferred programmed */
576 DMUB_FW_BOOT_STATUS_BIT_FAMS_ENABLED = (1 << 5), /**< 1 if FAMS is enabled*/
577 DMUB_FW_BOOT_STATUS_BIT_DETECTION_REQUIRED = (1 << 6), /**< 1 if detection need to be triggered by driver*/
578 DMUB_FW_BOOT_STATUS_BIT_HW_POWER_INIT_DONE = (1 << 7), /**< 1 if hw power init is completed */
579 };
580
581 /* Register bit definition for SCRATCH5 */
582 union dmub_lvtma_status {
583 struct {
584 uint32_t psp_ok : 1;
585 uint32_t edp_on : 1;
586 uint32_t reserved : 30;
587 } bits;
588 uint32_t all;
589 };
590
591 enum dmub_lvtma_status_bit {
592 DMUB_LVTMA_STATUS_BIT_PSP_OK = (1 << 0),
593 DMUB_LVTMA_STATUS_BIT_EDP_ON = (1 << 1),
594 };
595
596 enum dmub_ips_disable_type {
597 DMUB_IPS_DISABLE_IPS1 = 1,
598 DMUB_IPS_DISABLE_IPS2 = 2,
599 DMUB_IPS_DISABLE_IPS2_Z10 = 3,
600 };
601
602 /**
603 * union dmub_fw_boot_options - Boot option definitions for SCRATCH14
604 */
605 union dmub_fw_boot_options {
606 struct {
607 uint32_t pemu_env : 1; /**< 1 if PEMU */
608 uint32_t fpga_env : 1; /**< 1 if FPGA */
609 uint32_t optimized_init : 1; /**< 1 if optimized init */
610 uint32_t skip_phy_access : 1; /**< 1 if PHY access should be skipped */
611 uint32_t disable_clk_gate: 1; /**< 1 if clock gating should be disabled */
612 uint32_t skip_phy_init_panel_sequence: 1; /**< 1 to skip panel init seq */
613 uint32_t z10_disable: 1; /**< 1 to disable z10 */
614 uint32_t enable_dpia: 1; /**< 1 if DPIA should be enabled */
615 uint32_t invalid_vbios_data: 1; /**< 1 if VBIOS data table is invalid */
616 uint32_t dpia_supported: 1; /**< 1 if DPIA is supported on this platform */
617 uint32_t sel_mux_phy_c_d_phy_f_g: 1; /**< 1 if PHYF/PHYG should be enabled */
618 /**< 1 if all root clock gating is enabled and low power memory is enabled*/
619 uint32_t power_optimization: 1;
620 uint32_t diag_env: 1; /* 1 if diagnostic environment */
621 uint32_t gpint_scratch8: 1; /* 1 if GPINT is in scratch8*/
622 uint32_t usb4_cm_version: 1; /**< 1 CM support */
623 uint32_t dpia_hpd_int_enable_supported: 1; /* 1 if dpia hpd int enable supported */
624 uint32_t usb4_dpia_bw_alloc_supported: 1; /* 1 if USB4 dpia BW allocation supported */
625 uint32_t disable_clk_ds: 1; /* 1 if disallow dispclk_ds and dppclk_ds*/
626 uint32_t disable_timeout_recovery : 1; /* 1 if timeout recovery should be disabled */
627 uint32_t ips_pg_disable: 1; /* 1 to disable ONO domains power gating*/
628 uint32_t ips_disable: 2; /* options to disable ips support*/
629 uint32_t reserved : 10; /**< reserved */
630 } bits; /**< boot bits */
631 uint32_t all; /**< 32-bit access to bits */
632 };
633
634 enum dmub_fw_boot_options_bit {
635 DMUB_FW_BOOT_OPTION_BIT_PEMU_ENV = (1 << 0), /**< 1 if PEMU */
636 DMUB_FW_BOOT_OPTION_BIT_FPGA_ENV = (1 << 1), /**< 1 if FPGA */
637 DMUB_FW_BOOT_OPTION_BIT_OPTIMIZED_INIT_DONE = (1 << 2), /**< 1 if optimized init done */
638 };
639
640 //==============================================================================
641 //</DMUB_STATUS>================================================================
642 //==============================================================================
643 //< DMUB_VBIOS>=================================================================
644 //==============================================================================
645
646 /*
647 * enum dmub_cmd_vbios_type - VBIOS commands.
648 *
649 * Command IDs should be treated as stable ABI.
650 * Do not reuse or modify IDs.
651 */
652 enum dmub_cmd_vbios_type {
653 /**
654 * Configures the DIG encoder.
655 */
656 DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL = 0,
657 /**
658 * Controls the PHY.
659 */
660 DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL = 1,
661 /**
662 * Sets the pixel clock/symbol clock.
663 */
664 DMUB_CMD__VBIOS_SET_PIXEL_CLOCK = 2,
665 /**
666 * Enables or disables power gating.
667 */
668 DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING = 3,
669 /**
670 * Controls embedded panels.
671 */
672 DMUB_CMD__VBIOS_LVTMA_CONTROL = 15,
673 /**
674 * Query DP alt status on a transmitter.
675 */
676 DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT = 26,
677 /**
678 * Controls domain power gating
679 */
680 DMUB_CMD__VBIOS_DOMAIN_CONTROL = 28,
681 };
682
683 //==============================================================================
684 //</DMUB_VBIOS>=================================================================
685 //==============================================================================
686 //< DMUB_GPINT>=================================================================
687 //==============================================================================
688
689 /**
690 * The shifts and masks below may alternatively be used to format and read
691 * the command register bits.
692 */
693
694 #define DMUB_GPINT_DATA_PARAM_MASK 0xFFFF
695 #define DMUB_GPINT_DATA_PARAM_SHIFT 0
696
697 #define DMUB_GPINT_DATA_COMMAND_CODE_MASK 0xFFF
698 #define DMUB_GPINT_DATA_COMMAND_CODE_SHIFT 16
699
700 #define DMUB_GPINT_DATA_STATUS_MASK 0xF
701 #define DMUB_GPINT_DATA_STATUS_SHIFT 28
702
703 /**
704 * Command responses.
705 */
706
707 /**
708 * Return response for DMUB_GPINT__STOP_FW command.
709 */
710 #define DMUB_GPINT__STOP_FW_RESPONSE 0xDEADDEAD
711
712 /**
713 * union dmub_gpint_data_register - Format for sending a command via the GPINT.
714 */
715 union dmub_gpint_data_register {
716 struct {
717 uint32_t param : 16; /**< 16-bit parameter */
718 uint32_t command_code : 12; /**< GPINT command */
719 uint32_t status : 4; /**< Command status bit */
720 } bits; /**< GPINT bit access */
721 uint32_t all; /**< GPINT 32-bit access */
722 };
723
724 /*
725 * enum dmub_gpint_command - GPINT command to DMCUB FW
726 *
727 * Command IDs should be treated as stable ABI.
728 * Do not reuse or modify IDs.
729 */
730 enum dmub_gpint_command {
731 /**
732 * Invalid command, ignored.
733 */
734 DMUB_GPINT__INVALID_COMMAND = 0,
735 /**
736 * DESC: Queries the firmware version.
737 * RETURN: Firmware version.
738 */
739 DMUB_GPINT__GET_FW_VERSION = 1,
740 /**
741 * DESC: Halts the firmware.
742 * RETURN: DMUB_GPINT__STOP_FW_RESPONSE (0xDEADDEAD) when halted
743 */
744 DMUB_GPINT__STOP_FW = 2,
745 /**
746 * DESC: Get PSR state from FW.
747 * RETURN: PSR state enum. This enum may need to be converted to the legacy PSR state value.
748 */
749 DMUB_GPINT__GET_PSR_STATE = 7,
750 /**
751 * DESC: Notifies DMCUB of the currently active streams.
752 * ARGS: Stream mask, 1 bit per active stream index.
753 */
754 DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK = 8,
755 /**
756 * DESC: Start PSR residency counter. Stop PSR resdiency counter and get value.
757 * ARGS: We can measure residency from various points. The argument will specify the residency mode.
758 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY.
759 * RETURN: PSR residency in milli-percent.
760 */
761 DMUB_GPINT__PSR_RESIDENCY = 9,
762
763 /**
764 * DESC: Get REPLAY state from FW.
765 * RETURN: REPLAY state enum. This enum may need to be converted to the legacy REPLAY state value.
766 */
767 DMUB_GPINT__GET_REPLAY_STATE = 13,
768
769 /**
770 * DESC: Start REPLAY residency counter. Stop REPLAY resdiency counter and get value.
771 * ARGS: We can measure residency from various points. The argument will specify the residency mode.
772 * By default, it is measured from after we powerdown the PHY, to just before we powerup the PHY.
773 * RETURN: REPLAY residency in milli-percent.
774 */
775 DMUB_GPINT__REPLAY_RESIDENCY = 14,
776
777
778 /**
779 * DESC: Notifies DMCUB detection is done so detection required can be cleared.
780 */
781 DMUB_GPINT__NOTIFY_DETECTION_DONE = 12,
782 /**
783 * DESC: Updates the trace buffer lower 32-bit mask.
784 * ARGS: The new mask
785 * RETURN: Lower 32-bit mask.
786 */
787 DMUB_GPINT__UPDATE_TRACE_BUFFER_MASK = 101,
788 /**
789 * DESC: Updates the trace buffer lower 32-bit mask.
790 * ARGS: The new mask
791 * RETURN: Lower 32-bit mask.
792 */
793 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD0 = 102,
794 /**
795 * DESC: Updates the trace buffer mask bi0~bit15.
796 * ARGS: The new mask
797 * RETURN: Lower 32-bit mask.
798 */
799 DMUB_GPINT__SET_TRACE_BUFFER_MASK_WORD1 = 103,
800 };
801
802 /**
803 * INBOX0 generic command definition
804 */
805 union dmub_inbox0_cmd_common {
806 struct {
807 uint32_t command_code: 8; /**< INBOX0 command code */
808 uint32_t param: 24; /**< 24-bit parameter */
809 } bits;
810 uint32_t all;
811 };
812
813 /**
814 * INBOX0 hw_lock command definition
815 */
816 union dmub_inbox0_cmd_lock_hw {
817 struct {
818 uint32_t command_code: 8;
819
820 /* NOTE: Must be have enough bits to match: enum hw_lock_client */
821 uint32_t hw_lock_client: 2;
822
823 /* NOTE: Below fields must match with: struct dmub_hw_lock_inst_flags */
824 uint32_t otg_inst: 3;
825 uint32_t opp_inst: 3;
826 uint32_t dig_inst: 3;
827
828 /* NOTE: Below fields must match with: union dmub_hw_lock_flags */
829 uint32_t lock_pipe: 1;
830 uint32_t lock_cursor: 1;
831 uint32_t lock_dig: 1;
832 uint32_t triple_buffer_lock: 1;
833
834 uint32_t lock: 1; /**< Lock */
835 uint32_t should_release: 1; /**< Release */
836 uint32_t reserved: 7; /**< Reserved for extending more clients, HW, etc. */
837 } bits;
838 uint32_t all;
839 };
840
841 union dmub_inbox0_data_register {
842 union dmub_inbox0_cmd_common inbox0_cmd_common;
843 union dmub_inbox0_cmd_lock_hw inbox0_cmd_lock_hw;
844 };
845
846 enum dmub_inbox0_command {
847 /**
848 * DESC: Invalid command, ignored.
849 */
850 DMUB_INBOX0_CMD__INVALID_COMMAND = 0,
851 /**
852 * DESC: Notification to acquire/release HW lock
853 * ARGS:
854 */
855 DMUB_INBOX0_CMD__HW_LOCK = 1,
856 };
857 //==============================================================================
858 //</DMUB_GPINT>=================================================================
859 //==============================================================================
860 //< DMUB_CMD>===================================================================
861 //==============================================================================
862
863 /**
864 * Size in bytes of each DMUB command.
865 */
866 #define DMUB_RB_CMD_SIZE 64
867
868 /**
869 * Maximum number of items in the DMUB ringbuffer.
870 */
871 #define DMUB_RB_MAX_ENTRY 128
872
873 /**
874 * Ringbuffer size in bytes.
875 */
876 #define DMUB_RB_SIZE (DMUB_RB_CMD_SIZE * DMUB_RB_MAX_ENTRY)
877
878 /**
879 * REG_SET mask for reg offload.
880 */
881 #define REG_SET_MASK 0xFFFF
882
883 /*
884 * enum dmub_cmd_type - DMUB inbox command.
885 *
886 * Command IDs should be treated as stable ABI.
887 * Do not reuse or modify IDs.
888 */
889 enum dmub_cmd_type {
890 /**
891 * Invalid command.
892 */
893 DMUB_CMD__NULL = 0,
894 /**
895 * Read modify write register sequence offload.
896 */
897 DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE = 1,
898 /**
899 * Field update register sequence offload.
900 */
901 DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ = 2,
902 /**
903 * Burst write sequence offload.
904 */
905 DMUB_CMD__REG_SEQ_BURST_WRITE = 3,
906 /**
907 * Reg wait sequence offload.
908 */
909 DMUB_CMD__REG_REG_WAIT = 4,
910 /**
911 * Workaround to avoid HUBP underflow during NV12 playback.
912 */
913 DMUB_CMD__PLAT_54186_WA = 5,
914 /**
915 * Command type used to query FW feature caps.
916 */
917 DMUB_CMD__QUERY_FEATURE_CAPS = 6,
918 /**
919 * Command type used to get visual confirm color.
920 */
921 DMUB_CMD__GET_VISUAL_CONFIRM_COLOR = 8,
922 /**
923 * Command type used for all PSR commands.
924 */
925 DMUB_CMD__PSR = 64,
926 /**
927 * Command type used for all MALL commands.
928 */
929 DMUB_CMD__MALL = 65,
930 /**
931 * Command type used for all ABM commands.
932 */
933 DMUB_CMD__ABM = 66,
934 /**
935 * Command type used to update dirty rects in FW.
936 */
937 DMUB_CMD__UPDATE_DIRTY_RECT = 67,
938 /**
939 * Command type used to update cursor info in FW.
940 */
941 DMUB_CMD__UPDATE_CURSOR_INFO = 68,
942 /**
943 * Command type used for HW locking in FW.
944 */
945 DMUB_CMD__HW_LOCK = 69,
946 /**
947 * Command type used to access DP AUX.
948 */
949 DMUB_CMD__DP_AUX_ACCESS = 70,
950 /**
951 * Command type used for OUTBOX1 notification enable
952 */
953 DMUB_CMD__OUTBOX1_ENABLE = 71,
954
955 /**
956 * Command type used for all idle optimization commands.
957 */
958 DMUB_CMD__IDLE_OPT = 72,
959 /**
960 * Command type used for all clock manager commands.
961 */
962 DMUB_CMD__CLK_MGR = 73,
963 /**
964 * Command type used for all panel control commands.
965 */
966 DMUB_CMD__PANEL_CNTL = 74,
967 /**
968 * Command type used for <TODO:description>
969 */
970 DMUB_CMD__CAB_FOR_SS = 75,
971
972 DMUB_CMD__FW_ASSISTED_MCLK_SWITCH = 76,
973
974 /**
975 * Command type used for interfacing with DPIA.
976 */
977 DMUB_CMD__DPIA = 77,
978 /**
979 * Command type used for EDID CEA parsing
980 */
981 DMUB_CMD__EDID_CEA = 79,
982 /**
983 * Command type used for getting usbc cable ID
984 */
985 DMUB_CMD_GET_USBC_CABLE_ID = 81,
986 /**
987 * Command type used to query HPD state.
988 */
989 DMUB_CMD__QUERY_HPD_STATE = 82,
990 /**
991 * Command type used for all VBIOS interface commands.
992 */
993
994 /**
995 * Command type used for all REPLAY commands.
996 */
997 DMUB_CMD__REPLAY = 83,
998
999 /**
1000 * Command type used for all SECURE_DISPLAY commands.
1001 */
1002 DMUB_CMD__SECURE_DISPLAY = 85,
1003
1004 /**
1005 * Command type used to set DPIA HPD interrupt state
1006 */
1007 DMUB_CMD__DPIA_HPD_INT_ENABLE = 86,
1008
1009 DMUB_CMD__VBIOS = 128,
1010 };
1011
1012 /**
1013 * enum dmub_out_cmd_type - DMUB outbox commands.
1014 */
1015 enum dmub_out_cmd_type {
1016 /**
1017 * Invalid outbox command, ignored.
1018 */
1019 DMUB_OUT_CMD__NULL = 0,
1020 /**
1021 * Command type used for DP AUX Reply data notification
1022 */
1023 DMUB_OUT_CMD__DP_AUX_REPLY = 1,
1024 /**
1025 * Command type used for DP HPD event notification
1026 */
1027 DMUB_OUT_CMD__DP_HPD_NOTIFY = 2,
1028 /**
1029 * Command type used for SET_CONFIG Reply notification
1030 */
1031 DMUB_OUT_CMD__SET_CONFIG_REPLY = 3,
1032 /**
1033 * Command type used for USB4 DPIA notification
1034 */
1035 DMUB_OUT_CMD__DPIA_NOTIFICATION = 5,
1036 };
1037
1038 /* DMUB_CMD__DPIA command sub-types. */
1039 enum dmub_cmd_dpia_type {
1040 DMUB_CMD__DPIA_DIG1_DPIA_CONTROL = 0,
1041 DMUB_CMD__DPIA_SET_CONFIG_ACCESS = 1,
1042 DMUB_CMD__DPIA_MST_ALLOC_SLOTS = 2,
1043 };
1044
1045 /* DMUB_OUT_CMD__DPIA_NOTIFICATION command types. */
1046 enum dmub_cmd_dpia_notification_type {
1047 DPIA_NOTIFY__BW_ALLOCATION = 0,
1048 };
1049
1050 #pragma pack(push, 1)
1051
1052 /**
1053 * struct dmub_cmd_header - Common command header fields.
1054 */
1055 struct dmub_cmd_header {
1056 unsigned int type : 8; /**< command type */
1057 unsigned int sub_type : 8; /**< command sub type */
1058 unsigned int ret_status : 1; /**< 1 if returned data, 0 otherwise */
1059 unsigned int multi_cmd_pending : 1; /**< 1 if multiple commands chained together */
1060 unsigned int reserved0 : 6; /**< reserved bits */
1061 unsigned int payload_bytes : 6; /* payload excluding header - up to 60 bytes */
1062 unsigned int reserved1 : 2; /**< reserved bits */
1063 };
1064
1065 /*
1066 * struct dmub_cmd_read_modify_write_sequence - Read modify write
1067 *
1068 * 60 payload bytes can hold up to 5 sets of read modify writes,
1069 * each take 3 dwords.
1070 *
1071 * number of sequences = header.payload_bytes / sizeof(struct dmub_cmd_read_modify_write_sequence)
1072 *
1073 * modify_mask = 0xffff'ffff means all fields are going to be updated. in this case
1074 * command parser will skip the read and we can use modify_mask = 0xffff'ffff as reg write
1075 */
1076 struct dmub_cmd_read_modify_write_sequence {
1077 uint32_t addr; /**< register address */
1078 uint32_t modify_mask; /**< modify mask */
1079 uint32_t modify_value; /**< modify value */
1080 };
1081
1082 /**
1083 * Maximum number of ops in read modify write sequence.
1084 */
1085 #define DMUB_READ_MODIFY_WRITE_SEQ__MAX 5
1086
1087 /**
1088 * struct dmub_cmd_read_modify_write_sequence - Read modify write command.
1089 */
1090 struct dmub_rb_cmd_read_modify_write {
1091 struct dmub_cmd_header header; /**< command header */
1092 /**
1093 * Read modify write sequence.
1094 */
1095 struct dmub_cmd_read_modify_write_sequence seq[DMUB_READ_MODIFY_WRITE_SEQ__MAX];
1096 };
1097
1098 /*
1099 * Update a register with specified masks and values sequeunce
1100 *
1101 * 60 payload bytes can hold address + up to 7 sets of mask/value combo, each take 2 dword
1102 *
1103 * number of field update sequence = (header.payload_bytes - sizeof(addr)) / sizeof(struct read_modify_write_sequence)
1104 *
1105 *
1106 * USE CASE:
1107 * 1. auto-increment register where additional read would update pointer and produce wrong result
1108 * 2. toggle a bit without read in the middle
1109 */
1110
1111 struct dmub_cmd_reg_field_update_sequence {
1112 uint32_t modify_mask; /**< 0xffff'ffff to skip initial read */
1113 uint32_t modify_value; /**< value to update with */
1114 };
1115
1116 /**
1117 * Maximum number of ops in field update sequence.
1118 */
1119 #define DMUB_REG_FIELD_UPDATE_SEQ__MAX 7
1120
1121 /**
1122 * struct dmub_rb_cmd_reg_field_update_sequence - Field update command.
1123 */
1124 struct dmub_rb_cmd_reg_field_update_sequence {
1125 struct dmub_cmd_header header; /**< command header */
1126 uint32_t addr; /**< register address */
1127 /**
1128 * Field update sequence.
1129 */
1130 struct dmub_cmd_reg_field_update_sequence seq[DMUB_REG_FIELD_UPDATE_SEQ__MAX];
1131 };
1132
1133
1134 /**
1135 * Maximum number of burst write values.
1136 */
1137 #define DMUB_BURST_WRITE_VALUES__MAX 14
1138
1139 /*
1140 * struct dmub_rb_cmd_burst_write - Burst write
1141 *
1142 * support use case such as writing out LUTs.
1143 *
1144 * 60 payload bytes can hold up to 14 values to write to given address
1145 *
1146 * number of payload = header.payload_bytes / sizeof(struct read_modify_write_sequence)
1147 */
1148 struct dmub_rb_cmd_burst_write {
1149 struct dmub_cmd_header header; /**< command header */
1150 uint32_t addr; /**< register start address */
1151 /**
1152 * Burst write register values.
1153 */
1154 uint32_t write_values[DMUB_BURST_WRITE_VALUES__MAX];
1155 };
1156
1157 /**
1158 * struct dmub_rb_cmd_common - Common command header
1159 */
1160 struct dmub_rb_cmd_common {
1161 struct dmub_cmd_header header; /**< command header */
1162 /**
1163 * Padding to RB_CMD_SIZE
1164 */
1165 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)];
1166 };
1167
1168 /**
1169 * struct dmub_cmd_reg_wait_data - Register wait data
1170 */
1171 struct dmub_cmd_reg_wait_data {
1172 uint32_t addr; /**< Register address */
1173 uint32_t mask; /**< Mask for register bits */
1174 uint32_t condition_field_value; /**< Value to wait for */
1175 uint32_t time_out_us; /**< Time out for reg wait in microseconds */
1176 };
1177
1178 /**
1179 * struct dmub_rb_cmd_reg_wait - Register wait command
1180 */
1181 struct dmub_rb_cmd_reg_wait {
1182 struct dmub_cmd_header header; /**< Command header */
1183 struct dmub_cmd_reg_wait_data reg_wait; /**< Register wait data */
1184 };
1185
1186 /**
1187 * struct dmub_cmd_PLAT_54186_wa - Underflow workaround
1188 *
1189 * Reprograms surface parameters to avoid underflow.
1190 */
1191 struct dmub_cmd_PLAT_54186_wa {
1192 uint32_t DCSURF_SURFACE_CONTROL; /**< reg value */
1193 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH; /**< reg value */
1194 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS; /**< reg value */
1195 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_HIGH_C; /**< reg value */
1196 uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C; /**< reg value */
1197 struct {
1198 uint8_t hubp_inst : 4; /**< HUBP instance */
1199 uint8_t tmz_surface : 1; /**< TMZ enable or disable */
1200 uint8_t immediate :1; /**< Immediate flip */
1201 uint8_t vmid : 4; /**< VMID */
1202 uint8_t grph_stereo : 1; /**< 1 if stereo */
1203 uint32_t reserved : 21; /**< Reserved */
1204 } flip_params; /**< Pageflip parameters */
1205 uint32_t reserved[9]; /**< Reserved bits */
1206 };
1207
1208 /**
1209 * struct dmub_rb_cmd_PLAT_54186_wa - Underflow workaround command
1210 */
1211 struct dmub_rb_cmd_PLAT_54186_wa {
1212 struct dmub_cmd_header header; /**< Command header */
1213 struct dmub_cmd_PLAT_54186_wa flip; /**< Flip data */
1214 };
1215
1216 /**
1217 * struct dmub_rb_cmd_mall - MALL command data.
1218 */
1219 struct dmub_rb_cmd_mall {
1220 struct dmub_cmd_header header; /**< Common command header */
1221 union dmub_addr cursor_copy_src; /**< Cursor copy address */
1222 union dmub_addr cursor_copy_dst; /**< Cursor copy destination */
1223 uint32_t tmr_delay; /**< Timer delay */
1224 uint32_t tmr_scale; /**< Timer scale */
1225 uint16_t cursor_width; /**< Cursor width in pixels */
1226 uint16_t cursor_pitch; /**< Cursor pitch in pixels */
1227 uint16_t cursor_height; /**< Cursor height in pixels */
1228 uint8_t cursor_bpp; /**< Cursor bits per pixel */
1229 uint8_t debug_bits; /**< Debug bits */
1230
1231 uint8_t reserved1; /**< Reserved bits */
1232 uint8_t reserved2; /**< Reserved bits */
1233 };
1234
1235 /**
1236 * enum dmub_cmd_cab_type - CAB command data.
1237 */
1238 enum dmub_cmd_cab_type {
1239 /**
1240 * No idle optimizations (i.e. no CAB)
1241 */
1242 DMUB_CMD__CAB_NO_IDLE_OPTIMIZATION = 0,
1243 /**
1244 * No DCN requests for memory
1245 */
1246 DMUB_CMD__CAB_NO_DCN_REQ = 1,
1247 /**
1248 * Fit surfaces in CAB (i.e. CAB enable)
1249 */
1250 DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB = 2,
1251 };
1252
1253 /**
1254 * struct dmub_rb_cmd_cab - CAB command data.
1255 */
1256 struct dmub_rb_cmd_cab_for_ss {
1257 struct dmub_cmd_header header;
1258 uint8_t cab_alloc_ways; /* total number of ways */
1259 uint8_t debug_bits; /* debug bits */
1260 };
1261
1262 /**
1263 * Enum for indicating which MCLK switch mode per pipe
1264 */
1265 enum mclk_switch_mode {
1266 NONE = 0,
1267 FPO = 1,
1268 SUBVP = 2,
1269 VBLANK = 3,
1270 };
1271
1272 /* Per pipe struct which stores the MCLK switch mode
1273 * data to be sent to DMUB.
1274 * Named "v2" for now -- once FPO and SUBVP are fully merged
1275 * the type name can be updated
1276 */
1277 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 {
1278 union {
1279 struct {
1280 uint32_t pix_clk_100hz;
1281 uint16_t main_vblank_start;
1282 uint16_t main_vblank_end;
1283 uint16_t mall_region_lines;
1284 uint16_t prefetch_lines;
1285 uint16_t prefetch_to_mall_start_lines;
1286 uint16_t processing_delay_lines;
1287 uint16_t htotal; // required to calculate line time for multi-display cases
1288 uint16_t vtotal;
1289 uint8_t main_pipe_index;
1290 uint8_t phantom_pipe_index;
1291 /* Since the microschedule is calculated in terms of OTG lines,
1292 * include any scaling factors to make sure when we get accurate
1293 * conversion when programming MALL_START_LINE (which is in terms
1294 * of HUBP lines). If 4K is being downscaled to 1080p, scale factor
1295 * is 1/2 (numerator = 1, denominator = 2).
1296 */
1297 uint8_t scale_factor_numerator;
1298 uint8_t scale_factor_denominator;
1299 uint8_t is_drr;
1300 uint8_t main_split_pipe_index;
1301 uint8_t phantom_split_pipe_index;
1302 } subvp_data;
1303
1304 struct {
1305 uint32_t pix_clk_100hz;
1306 uint16_t vblank_start;
1307 uint16_t vblank_end;
1308 uint16_t vstartup_start;
1309 uint16_t vtotal;
1310 uint16_t htotal;
1311 uint8_t vblank_pipe_index;
1312 uint8_t padding[1];
1313 struct {
1314 uint8_t drr_in_use;
1315 uint8_t drr_window_size_ms; // Indicates largest VMIN/VMAX adjustment per frame
1316 uint16_t min_vtotal_supported; // Min VTOTAL that supports switching in VBLANK
1317 uint16_t max_vtotal_supported; // Max VTOTAL that can support SubVP static scheduling
1318 uint8_t use_ramping; // Use ramping or not
1319 uint8_t drr_vblank_start_margin;
1320 } drr_info; // DRR considered as part of SubVP + VBLANK case
1321 } vblank_data;
1322 } pipe_config;
1323
1324 /* - subvp_data in the union (pipe_config) takes up 27 bytes.
1325 * - Make the "mode" field a uint8_t instead of enum so we only use 1 byte (only
1326 * for the DMCUB command, cast to enum once we populate the DMCUB subvp state).
1327 */
1328 uint8_t mode; // enum mclk_switch_mode
1329 };
1330
1331 /**
1332 * Config data for Sub-VP and FPO
1333 * Named "v2" for now -- once FPO and SUBVP are fully merged
1334 * the type name can be updated
1335 */
1336 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 {
1337 uint16_t watermark_a_cache;
1338 uint8_t vertical_int_margin_us;
1339 uint8_t pstate_allow_width_us;
1340 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data_v2 pipe_data[DMUB_MAX_SUBVP_STREAMS];
1341 };
1342
1343 /**
1344 * DMUB rb command definition for Sub-VP and FPO
1345 * Named "v2" for now -- once FPO and SUBVP are fully merged
1346 * the type name can be updated
1347 */
1348 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 {
1349 struct dmub_cmd_header header;
1350 struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data;
1351 };
1352
1353 /**
1354 * enum dmub_cmd_idle_opt_type - Idle optimization command type.
1355 */
1356 enum dmub_cmd_idle_opt_type {
1357 /**
1358 * DCN hardware restore.
1359 */
1360 DMUB_CMD__IDLE_OPT_DCN_RESTORE = 0,
1361
1362 /**
1363 * DCN hardware save.
1364 */
1365 DMUB_CMD__IDLE_OPT_DCN_SAVE_INIT = 1,
1366
1367 /**
1368 * DCN hardware notify idle.
1369 */
1370 DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE = 2
1371 };
1372
1373 /**
1374 * struct dmub_rb_cmd_idle_opt_dcn_restore - DCN restore command data.
1375 */
1376 struct dmub_rb_cmd_idle_opt_dcn_restore {
1377 struct dmub_cmd_header header; /**< header */
1378 };
1379
1380 /**
1381 * struct dmub_dcn_notify_idle_cntl_data - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command.
1382 */
1383 struct dmub_dcn_notify_idle_cntl_data {
1384 uint8_t driver_idle;
1385 uint8_t pad[1];
1386 };
1387
1388 /**
1389 * struct dmub_rb_cmd_idle_opt_dcn_notify_idle - Data passed to FW in a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command.
1390 */
1391 struct dmub_rb_cmd_idle_opt_dcn_notify_idle {
1392 struct dmub_cmd_header header; /**< header */
1393 struct dmub_dcn_notify_idle_cntl_data cntl_data;
1394 };
1395
1396 /**
1397 * struct dmub_clocks - Clock update notification.
1398 */
1399 struct dmub_clocks {
1400 uint32_t dispclk_khz; /**< dispclk kHz */
1401 uint32_t dppclk_khz; /**< dppclk kHz */
1402 uint32_t dcfclk_khz; /**< dcfclk kHz */
1403 uint32_t dcfclk_deep_sleep_khz; /**< dcfclk deep sleep kHz */
1404 };
1405
1406 /**
1407 * enum dmub_cmd_clk_mgr_type - Clock manager commands.
1408 */
1409 enum dmub_cmd_clk_mgr_type {
1410 /**
1411 * Notify DMCUB of clock update.
1412 */
1413 DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS = 0,
1414 };
1415
1416 /**
1417 * struct dmub_rb_cmd_clk_mgr_notify_clocks - Clock update notification.
1418 */
1419 struct dmub_rb_cmd_clk_mgr_notify_clocks {
1420 struct dmub_cmd_header header; /**< header */
1421 struct dmub_clocks clocks; /**< clock data */
1422 };
1423
1424 /**
1425 * struct dmub_cmd_digx_encoder_control_data - Encoder control data.
1426 */
1427 struct dmub_cmd_digx_encoder_control_data {
1428 union dig_encoder_control_parameters_v1_5 dig; /**< payload */
1429 };
1430
1431 /**
1432 * struct dmub_rb_cmd_digx_encoder_control - Encoder control command.
1433 */
1434 struct dmub_rb_cmd_digx_encoder_control {
1435 struct dmub_cmd_header header; /**< header */
1436 struct dmub_cmd_digx_encoder_control_data encoder_control; /**< payload */
1437 };
1438
1439 /**
1440 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock data.
1441 */
1442 struct dmub_cmd_set_pixel_clock_data {
1443 struct set_pixel_clock_parameter_v1_7 clk; /**< payload */
1444 };
1445
1446 /**
1447 * struct dmub_cmd_set_pixel_clock_data - Set pixel clock command.
1448 */
1449 struct dmub_rb_cmd_set_pixel_clock {
1450 struct dmub_cmd_header header; /**< header */
1451 struct dmub_cmd_set_pixel_clock_data pixel_clock; /**< payload */
1452 };
1453
1454 /**
1455 * struct dmub_cmd_enable_disp_power_gating_data - Display power gating.
1456 */
1457 struct dmub_cmd_enable_disp_power_gating_data {
1458 struct enable_disp_power_gating_parameters_v2_1 pwr; /**< payload */
1459 };
1460
1461 /**
1462 * struct dmub_rb_cmd_enable_disp_power_gating - Display power command.
1463 */
1464 struct dmub_rb_cmd_enable_disp_power_gating {
1465 struct dmub_cmd_header header; /**< header */
1466 struct dmub_cmd_enable_disp_power_gating_data power_gating; /**< payload */
1467 };
1468
1469 /**
1470 * struct dmub_dig_transmitter_control_data_v1_7 - Transmitter control.
1471 */
1472 struct dmub_dig_transmitter_control_data_v1_7 {
1473 uint8_t phyid; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */
1474 uint8_t action; /**< Defined as ATOM_TRANSMITER_ACTION_xxx */
1475 union {
1476 uint8_t digmode; /**< enum atom_encode_mode_def */
1477 uint8_t dplaneset; /**< DP voltage swing and pre-emphasis value, "DP_LANE_SET__xDB_y_zV" */
1478 } mode_laneset;
1479 uint8_t lanenum; /**< Number of lanes */
1480 union {
1481 uint32_t symclk_10khz; /**< Symbol Clock in 10Khz */
1482 } symclk_units;
1483 uint8_t hpdsel; /**< =1: HPD1, =2: HPD2, ..., =6: HPD6, =0: HPD is not assigned */
1484 uint8_t digfe_sel; /**< DIG front-end selection, bit0 means DIG0 FE is enabled */
1485 uint8_t connobj_id; /**< Connector Object Id defined in ObjectId.h */
1486 uint8_t HPO_instance; /**< HPO instance (0: inst0, 1: inst1) */
1487 uint8_t reserved1; /**< For future use */
1488 uint8_t reserved2[3]; /**< For future use */
1489 uint32_t reserved3[11]; /**< For future use */
1490 };
1491
1492 /**
1493 * union dmub_cmd_dig1_transmitter_control_data - Transmitter control data.
1494 */
1495 union dmub_cmd_dig1_transmitter_control_data {
1496 struct dig_transmitter_control_parameters_v1_6 dig; /**< payload */
1497 struct dmub_dig_transmitter_control_data_v1_7 dig_v1_7; /**< payload 1.7 */
1498 };
1499
1500 /**
1501 * struct dmub_rb_cmd_dig1_transmitter_control - Transmitter control command.
1502 */
1503 struct dmub_rb_cmd_dig1_transmitter_control {
1504 struct dmub_cmd_header header; /**< header */
1505 union dmub_cmd_dig1_transmitter_control_data transmitter_control; /**< payload */
1506 };
1507
1508 /**
1509 * struct dmub_rb_cmd_domain_control_data - Data for DOMAIN power control
1510 */
1511 struct dmub_rb_cmd_domain_control_data {
1512 uint8_t inst : 6; /**< DOMAIN instance to control */
1513 uint8_t power_gate : 1; /**< 1=power gate, 0=power up */
1514 uint8_t reserved[3]; /**< Reserved for future use */
1515 };
1516
1517 /**
1518 * struct dmub_rb_cmd_domain_control - Controls DOMAIN power gating
1519 */
1520 struct dmub_rb_cmd_domain_control {
1521 struct dmub_cmd_header header; /**< header */
1522 struct dmub_rb_cmd_domain_control_data data; /**< payload */
1523 };
1524
1525 /**
1526 * DPIA tunnel command parameters.
1527 */
1528 struct dmub_cmd_dig_dpia_control_data {
1529 uint8_t enc_id; /** 0 = ENGINE_ID_DIGA, ... */
1530 uint8_t action; /** ATOM_TRANSMITER_ACTION_DISABLE/ENABLE/SETUP_VSEMPH */
1531 union {
1532 uint8_t digmode; /** enum atom_encode_mode_def */
1533 uint8_t dplaneset; /** DP voltage swing and pre-emphasis value */
1534 } mode_laneset;
1535 uint8_t lanenum; /** Lane number 1, 2, 4, 8 */
1536 uint32_t symclk_10khz; /** Symbol Clock in 10Khz */
1537 uint8_t hpdsel; /** =0: HPD is not assigned */
1538 uint8_t digfe_sel; /** DIG stream( front-end ) selection, bit0 - DIG0 FE */
1539 uint8_t dpia_id; /** Index of DPIA */
1540 uint8_t fec_rdy : 1;
1541 uint8_t reserved : 7;
1542 uint32_t reserved1;
1543 };
1544
1545 /**
1546 * DMUB command for DPIA tunnel control.
1547 */
1548 struct dmub_rb_cmd_dig1_dpia_control {
1549 struct dmub_cmd_header header;
1550 struct dmub_cmd_dig_dpia_control_data dpia_control;
1551 };
1552
1553 /**
1554 * SET_CONFIG Command Payload
1555 */
1556 struct set_config_cmd_payload {
1557 uint8_t msg_type; /* set config message type */
1558 uint8_t msg_data; /* set config message data */
1559 };
1560
1561 /**
1562 * Data passed from driver to FW in a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command.
1563 */
1564 struct dmub_cmd_set_config_control_data {
1565 struct set_config_cmd_payload cmd_pkt;
1566 uint8_t instance; /* DPIA instance */
1567 uint8_t immed_status; /* Immediate status returned in case of error */
1568 };
1569
1570 /**
1571 * DMUB command structure for SET_CONFIG command.
1572 */
1573 struct dmub_rb_cmd_set_config_access {
1574 struct dmub_cmd_header header; /* header */
1575 struct dmub_cmd_set_config_control_data set_config_control; /* set config data */
1576 };
1577
1578 /**
1579 * Data passed from driver to FW in a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command.
1580 */
1581 struct dmub_cmd_mst_alloc_slots_control_data {
1582 uint8_t mst_alloc_slots; /* mst slots to be allotted */
1583 uint8_t instance; /* DPIA instance */
1584 uint8_t immed_status; /* Immediate status returned as there is no outbox msg posted */
1585 uint8_t mst_slots_in_use; /* returns slots in use for error cases */
1586 };
1587
1588 /**
1589 * DMUB command structure for SET_ command.
1590 */
1591 struct dmub_rb_cmd_set_mst_alloc_slots {
1592 struct dmub_cmd_header header; /* header */
1593 struct dmub_cmd_mst_alloc_slots_control_data mst_slots_control; /* mst slots control */
1594 };
1595
1596 /**
1597 * DMUB command structure for DPIA HPD int enable control.
1598 */
1599 struct dmub_rb_cmd_dpia_hpd_int_enable {
1600 struct dmub_cmd_header header; /* header */
1601 uint32_t enable; /* dpia hpd interrupt enable */
1602 };
1603
1604 /**
1605 * struct dmub_rb_cmd_dpphy_init - DPPHY init.
1606 */
1607 struct dmub_rb_cmd_dpphy_init {
1608 struct dmub_cmd_header header; /**< header */
1609 uint8_t reserved[60]; /**< reserved bits */
1610 };
1611
1612 /**
1613 * enum dp_aux_request_action - DP AUX request command listing.
1614 *
1615 * 4 AUX request command bits are shifted to high nibble.
1616 */
1617 enum dp_aux_request_action {
1618 /** I2C-over-AUX write request */
1619 DP_AUX_REQ_ACTION_I2C_WRITE = 0x00,
1620 /** I2C-over-AUX read request */
1621 DP_AUX_REQ_ACTION_I2C_READ = 0x10,
1622 /** I2C-over-AUX write status request */
1623 DP_AUX_REQ_ACTION_I2C_STATUS_REQ = 0x20,
1624 /** I2C-over-AUX write request with MOT=1 */
1625 DP_AUX_REQ_ACTION_I2C_WRITE_MOT = 0x40,
1626 /** I2C-over-AUX read request with MOT=1 */
1627 DP_AUX_REQ_ACTION_I2C_READ_MOT = 0x50,
1628 /** I2C-over-AUX write status request with MOT=1 */
1629 DP_AUX_REQ_ACTION_I2C_STATUS_REQ_MOT = 0x60,
1630 /** Native AUX write request */
1631 DP_AUX_REQ_ACTION_DPCD_WRITE = 0x80,
1632 /** Native AUX read request */
1633 DP_AUX_REQ_ACTION_DPCD_READ = 0x90
1634 };
1635
1636 /**
1637 * enum aux_return_code_type - DP AUX process return code listing.
1638 */
1639 enum aux_return_code_type {
1640 /** AUX process succeeded */
1641 AUX_RET_SUCCESS = 0,
1642 /** AUX process failed with unknown reason */
1643 AUX_RET_ERROR_UNKNOWN,
1644 /** AUX process completed with invalid reply */
1645 AUX_RET_ERROR_INVALID_REPLY,
1646 /** AUX process timed out */
1647 AUX_RET_ERROR_TIMEOUT,
1648 /** HPD was low during AUX process */
1649 AUX_RET_ERROR_HPD_DISCON,
1650 /** Failed to acquire AUX engine */
1651 AUX_RET_ERROR_ENGINE_ACQUIRE,
1652 /** AUX request not supported */
1653 AUX_RET_ERROR_INVALID_OPERATION,
1654 /** AUX process not available */
1655 AUX_RET_ERROR_PROTOCOL_ERROR,
1656 };
1657
1658 /**
1659 * enum aux_channel_type - DP AUX channel type listing.
1660 */
1661 enum aux_channel_type {
1662 /** AUX thru Legacy DP AUX */
1663 AUX_CHANNEL_LEGACY_DDC,
1664 /** AUX thru DPIA DP tunneling */
1665 AUX_CHANNEL_DPIA
1666 };
1667
1668 /**
1669 * struct aux_transaction_parameters - DP AUX request transaction data
1670 */
1671 struct aux_transaction_parameters {
1672 uint8_t is_i2c_over_aux; /**< 0=native AUX, 1=I2C-over-AUX */
1673 uint8_t action; /**< enum dp_aux_request_action */
1674 uint8_t length; /**< DP AUX request data length */
1675 uint8_t reserved; /**< For future use */
1676 uint32_t address; /**< DP AUX address */
1677 uint8_t data[16]; /**< DP AUX write data */
1678 };
1679
1680 /**
1681 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command.
1682 */
1683 struct dmub_cmd_dp_aux_control_data {
1684 uint8_t instance; /**< AUX instance or DPIA instance */
1685 uint8_t manual_acq_rel_enable; /**< manual control for acquiring or releasing AUX channel */
1686 uint8_t sw_crc_enabled; /**< Use software CRC for tunneling packet instead of hardware CRC */
1687 uint8_t reserved0; /**< For future use */
1688 uint16_t timeout; /**< timeout time in us */
1689 uint16_t reserved1; /**< For future use */
1690 enum aux_channel_type type; /**< enum aux_channel_type */
1691 struct aux_transaction_parameters dpaux; /**< struct aux_transaction_parameters */
1692 };
1693
1694 /**
1695 * Definition of a DMUB_CMD__DP_AUX_ACCESS command.
1696 */
1697 struct dmub_rb_cmd_dp_aux_access {
1698 /**
1699 * Command header.
1700 */
1701 struct dmub_cmd_header header;
1702 /**
1703 * Data passed from driver to FW in a DMUB_CMD__DP_AUX_ACCESS command.
1704 */
1705 struct dmub_cmd_dp_aux_control_data aux_control;
1706 };
1707
1708 /**
1709 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command.
1710 */
1711 struct dmub_rb_cmd_outbox1_enable {
1712 /**
1713 * Command header.
1714 */
1715 struct dmub_cmd_header header;
1716 /**
1717 * enable: 0x0 -> disable outbox1 notification (default value)
1718 * 0x1 -> enable outbox1 notification
1719 */
1720 uint32_t enable;
1721 };
1722
1723 /* DP AUX Reply command - OutBox Cmd */
1724 /**
1725 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
1726 */
1727 struct aux_reply_data {
1728 /**
1729 * Aux cmd
1730 */
1731 uint8_t command;
1732 /**
1733 * Aux reply data length (max: 16 bytes)
1734 */
1735 uint8_t length;
1736 /**
1737 * Alignment only
1738 */
1739 uint8_t pad[2];
1740 /**
1741 * Aux reply data
1742 */
1743 uint8_t data[16];
1744 };
1745
1746 /**
1747 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
1748 */
1749 struct aux_reply_control_data {
1750 /**
1751 * Reserved for future use
1752 */
1753 uint32_t handle;
1754 /**
1755 * Aux Instance
1756 */
1757 uint8_t instance;
1758 /**
1759 * Aux transaction result: definition in enum aux_return_code_type
1760 */
1761 uint8_t result;
1762 /**
1763 * Alignment only
1764 */
1765 uint16_t pad;
1766 };
1767
1768 /**
1769 * Definition of a DMUB_OUT_CMD__DP_AUX_REPLY command.
1770 */
1771 struct dmub_rb_cmd_dp_aux_reply {
1772 /**
1773 * Command header.
1774 */
1775 struct dmub_cmd_header header;
1776 /**
1777 * Control Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
1778 */
1779 struct aux_reply_control_data control;
1780 /**
1781 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_AUX_REPLY command.
1782 */
1783 struct aux_reply_data reply_data;
1784 };
1785
1786 /* DP HPD Notify command - OutBox Cmd */
1787 /**
1788 * DP HPD Type
1789 */
1790 enum dp_hpd_type {
1791 /**
1792 * Normal DP HPD
1793 */
1794 DP_HPD = 0,
1795 /**
1796 * DP HPD short pulse
1797 */
1798 DP_IRQ
1799 };
1800
1801 /**
1802 * DP HPD Status
1803 */
1804 enum dp_hpd_status {
1805 /**
1806 * DP_HPD status low
1807 */
1808 DP_HPD_UNPLUG = 0,
1809 /**
1810 * DP_HPD status high
1811 */
1812 DP_HPD_PLUG
1813 };
1814
1815 /**
1816 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command.
1817 */
1818 struct dp_hpd_data {
1819 /**
1820 * DP HPD instance
1821 */
1822 uint8_t instance;
1823 /**
1824 * HPD type
1825 */
1826 uint8_t hpd_type;
1827 /**
1828 * HPD status: only for type: DP_HPD to indicate status
1829 */
1830 uint8_t hpd_status;
1831 /**
1832 * Alignment only
1833 */
1834 uint8_t pad;
1835 };
1836
1837 /**
1838 * Definition of a DMUB_OUT_CMD__DP_HPD_NOTIFY command.
1839 */
1840 struct dmub_rb_cmd_dp_hpd_notify {
1841 /**
1842 * Command header.
1843 */
1844 struct dmub_cmd_header header;
1845 /**
1846 * Data passed to driver from FW in a DMUB_OUT_CMD__DP_HPD_NOTIFY command.
1847 */
1848 struct dp_hpd_data hpd_data;
1849 };
1850
1851 /**
1852 * Definition of a SET_CONFIG reply from DPOA.
1853 */
1854 enum set_config_status {
1855 SET_CONFIG_PENDING = 0,
1856 SET_CONFIG_ACK_RECEIVED,
1857 SET_CONFIG_RX_TIMEOUT,
1858 SET_CONFIG_UNKNOWN_ERROR,
1859 };
1860
1861 /**
1862 * Definition of a set_config reply
1863 */
1864 struct set_config_reply_control_data {
1865 uint8_t instance; /* DPIA Instance */
1866 uint8_t status; /* Set Config reply */
1867 uint16_t pad; /* Alignment */
1868 };
1869
1870 /**
1871 * Definition of a DMUB_OUT_CMD__SET_CONFIG_REPLY command.
1872 */
1873 struct dmub_rb_cmd_dp_set_config_reply {
1874 struct dmub_cmd_header header;
1875 struct set_config_reply_control_data set_config_reply_control;
1876 };
1877
1878 /**
1879 * Definition of a DPIA notification header
1880 */
1881 struct dpia_notification_header {
1882 uint8_t instance; /**< DPIA Instance */
1883 uint8_t reserved[3];
1884 enum dmub_cmd_dpia_notification_type type; /**< DPIA notification type */
1885 };
1886
1887 /**
1888 * Definition of the common data struct of DPIA notification
1889 */
1890 struct dpia_notification_common {
1891 uint8_t cmd_buffer[DMUB_RB_CMD_SIZE - sizeof(struct dmub_cmd_header)
1892 - sizeof(struct dpia_notification_header)];
1893 };
1894
1895 /**
1896 * Definition of a DPIA notification data
1897 */
1898 struct dpia_bw_allocation_notify_data {
1899 union {
1900 struct {
1901 uint16_t cm_bw_alloc_support: 1; /**< USB4 CM BW Allocation mode support */
1902 uint16_t bw_request_failed: 1; /**< BW_Request_Failed */
1903 uint16_t bw_request_succeeded: 1; /**< BW_Request_Succeeded */
1904 uint16_t est_bw_changed: 1; /**< Estimated_BW changed */
1905 uint16_t bw_alloc_cap_changed: 1; /**< BW_Allocation_Capabiity_Changed */
1906 uint16_t reserved: 11; /**< Reserved */
1907 } bits;
1908
1909 uint16_t flags;
1910 };
1911
1912 uint8_t cm_id; /**< CM ID */
1913 uint8_t group_id; /**< Group ID */
1914 uint8_t granularity; /**< BW Allocation Granularity */
1915 uint8_t estimated_bw; /**< Estimated_BW */
1916 uint8_t allocated_bw; /**< Allocated_BW */
1917 uint8_t reserved;
1918 };
1919
1920 /**
1921 * union dpia_notify_data_type - DPIA Notification in Outbox command
1922 */
1923 union dpia_notification_data {
1924 /**
1925 * DPIA Notification for common data struct
1926 */
1927 struct dpia_notification_common common_data;
1928
1929 /**
1930 * DPIA Notification for DP BW Allocation support
1931 */
1932 struct dpia_bw_allocation_notify_data dpia_bw_alloc;
1933 };
1934
1935 /**
1936 * Definition of a DPIA notification payload
1937 */
1938 struct dpia_notification_payload {
1939 struct dpia_notification_header header;
1940 union dpia_notification_data data; /**< DPIA notification payload data */
1941 };
1942
1943 /**
1944 * Definition of a DMUB_OUT_CMD__DPIA_NOTIFICATION command.
1945 */
1946 struct dmub_rb_cmd_dpia_notification {
1947 struct dmub_cmd_header header; /**< DPIA notification header */
1948 struct dpia_notification_payload payload; /**< DPIA notification payload */
1949 };
1950
1951 /**
1952 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command.
1953 */
1954 struct dmub_cmd_hpd_state_query_data {
1955 uint8_t instance; /**< HPD instance or DPIA instance */
1956 uint8_t result; /**< For returning HPD state */
1957 uint16_t pad; /** < Alignment */
1958 enum aux_channel_type ch_type; /**< enum aux_channel_type */
1959 enum aux_return_code_type status; /**< for returning the status of command */
1960 };
1961
1962 /**
1963 * Definition of a DMUB_CMD__QUERY_HPD_STATE command.
1964 */
1965 struct dmub_rb_cmd_query_hpd_state {
1966 /**
1967 * Command header.
1968 */
1969 struct dmub_cmd_header header;
1970 /**
1971 * Data passed from driver to FW in a DMUB_CMD__QUERY_HPD_STATE command.
1972 */
1973 struct dmub_cmd_hpd_state_query_data data;
1974 };
1975
1976 /*
1977 * Command IDs should be treated as stable ABI.
1978 * Do not reuse or modify IDs.
1979 */
1980
1981 /**
1982 * PSR command sub-types.
1983 */
1984 enum dmub_cmd_psr_type {
1985 /**
1986 * Set PSR version support.
1987 */
1988 DMUB_CMD__PSR_SET_VERSION = 0,
1989 /**
1990 * Copy driver-calculated parameters to PSR state.
1991 */
1992 DMUB_CMD__PSR_COPY_SETTINGS = 1,
1993 /**
1994 * Enable PSR.
1995 */
1996 DMUB_CMD__PSR_ENABLE = 2,
1997
1998 /**
1999 * Disable PSR.
2000 */
2001 DMUB_CMD__PSR_DISABLE = 3,
2002
2003 /**
2004 * Set PSR level.
2005 * PSR level is a 16-bit value dicated by driver that
2006 * will enable/disable different functionality.
2007 */
2008 DMUB_CMD__PSR_SET_LEVEL = 4,
2009
2010 /**
2011 * Forces PSR enabled until an explicit PSR disable call.
2012 */
2013 DMUB_CMD__PSR_FORCE_STATIC = 5,
2014 /**
2015 * Set vtotal in psr active for FreeSync PSR.
2016 */
2017 DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE = 6,
2018 /**
2019 * Set PSR power option
2020 */
2021 DMUB_CMD__SET_PSR_POWER_OPT = 7,
2022 };
2023
2024 enum dmub_cmd_fams_type {
2025 DMUB_CMD__FAMS_SETUP_FW_CTRL = 0,
2026 DMUB_CMD__FAMS_DRR_UPDATE = 1,
2027 DMUB_CMD__HANDLE_SUBVP_CMD = 2, // specifically for SubVP cmd
2028 /**
2029 * For SubVP set manual trigger in FW because it
2030 * triggers DRR_UPDATE_PENDING which SubVP relies
2031 * on (for any SubVP cases that use a DRR display)
2032 */
2033 DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3,
2034 };
2035
2036 /**
2037 * PSR versions.
2038 */
2039 enum psr_version {
2040 /**
2041 * PSR version 1.
2042 */
2043 PSR_VERSION_1 = 0,
2044 /**
2045 * Freesync PSR SU.
2046 */
2047 PSR_VERSION_SU_1 = 1,
2048 /**
2049 * PSR not supported.
2050 */
2051 PSR_VERSION_UNSUPPORTED = 0xFFFFFFFF,
2052 };
2053
2054 /**
2055 * enum dmub_cmd_mall_type - MALL commands
2056 */
2057 enum dmub_cmd_mall_type {
2058 /**
2059 * Allows display refresh from MALL.
2060 */
2061 DMUB_CMD__MALL_ACTION_ALLOW = 0,
2062 /**
2063 * Disallows display refresh from MALL.
2064 */
2065 DMUB_CMD__MALL_ACTION_DISALLOW = 1,
2066 /**
2067 * Cursor copy for MALL.
2068 */
2069 DMUB_CMD__MALL_ACTION_COPY_CURSOR = 2,
2070 /**
2071 * Controls DF requests.
2072 */
2073 DMUB_CMD__MALL_ACTION_NO_DF_REQ = 3,
2074 };
2075
2076 /**
2077 * PHY Link rate for DP.
2078 */
2079 enum phy_link_rate {
2080 /**
2081 * not supported.
2082 */
2083 PHY_RATE_UNKNOWN = 0,
2084 /**
2085 * Rate_1 (RBR) - 1.62 Gbps/Lane
2086 */
2087 PHY_RATE_162 = 1,
2088 /**
2089 * Rate_2 - 2.16 Gbps/Lane
2090 */
2091 PHY_RATE_216 = 2,
2092 /**
2093 * Rate_3 - 2.43 Gbps/Lane
2094 */
2095 PHY_RATE_243 = 3,
2096 /**
2097 * Rate_4 (HBR) - 2.70 Gbps/Lane
2098 */
2099 PHY_RATE_270 = 4,
2100 /**
2101 * Rate_5 (RBR2)- 3.24 Gbps/Lane
2102 */
2103 PHY_RATE_324 = 5,
2104 /**
2105 * Rate_6 - 4.32 Gbps/Lane
2106 */
2107 PHY_RATE_432 = 6,
2108 /**
2109 * Rate_7 (HBR2)- 5.40 Gbps/Lane
2110 */
2111 PHY_RATE_540 = 7,
2112 /**
2113 * Rate_8 (HBR3)- 8.10 Gbps/Lane
2114 */
2115 PHY_RATE_810 = 8,
2116 /**
2117 * UHBR10 - 10.0 Gbps/Lane
2118 */
2119 PHY_RATE_1000 = 9,
2120 /**
2121 * UHBR13.5 - 13.5 Gbps/Lane
2122 */
2123 PHY_RATE_1350 = 10,
2124 /**
2125 * UHBR10 - 20.0 Gbps/Lane
2126 */
2127 PHY_RATE_2000 = 11,
2128 };
2129
2130 /**
2131 * enum dmub_phy_fsm_state - PHY FSM states.
2132 * PHY FSM state to transit to during PSR enable/disable.
2133 */
2134 enum dmub_phy_fsm_state {
2135 DMUB_PHY_FSM_POWER_UP_DEFAULT = 0,
2136 DMUB_PHY_FSM_RESET,
2137 DMUB_PHY_FSM_RESET_RELEASED,
2138 DMUB_PHY_FSM_SRAM_LOAD_DONE,
2139 DMUB_PHY_FSM_INITIALIZED,
2140 DMUB_PHY_FSM_CALIBRATED,
2141 DMUB_PHY_FSM_CALIBRATED_LP,
2142 DMUB_PHY_FSM_CALIBRATED_PG,
2143 DMUB_PHY_FSM_POWER_DOWN,
2144 DMUB_PHY_FSM_PLL_EN,
2145 DMUB_PHY_FSM_TX_EN,
2146 DMUB_PHY_FSM_FAST_LP,
2147 DMUB_PHY_FSM_P2_PLL_OFF_CPM,
2148 DMUB_PHY_FSM_P2_PLL_OFF_PG,
2149 DMUB_PHY_FSM_P2_PLL_OFF,
2150 DMUB_PHY_FSM_P2_PLL_ON,
2151 };
2152
2153 /**
2154 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command.
2155 */
2156 struct dmub_cmd_psr_copy_settings_data {
2157 /**
2158 * Flags that can be set by driver to change some PSR behaviour.
2159 */
2160 union dmub_psr_debug_flags debug;
2161 /**
2162 * 16-bit value dicated by driver that will enable/disable different functionality.
2163 */
2164 uint16_t psr_level;
2165 /**
2166 * DPP HW instance.
2167 */
2168 uint8_t dpp_inst;
2169 /**
2170 * MPCC HW instance.
2171 * Not used in dmub fw,
2172 * dmub fw will get active opp by reading odm registers.
2173 */
2174 uint8_t mpcc_inst;
2175 /**
2176 * OPP HW instance.
2177 * Not used in dmub fw,
2178 * dmub fw will get active opp by reading odm registers.
2179 */
2180 uint8_t opp_inst;
2181 /**
2182 * OTG HW instance.
2183 */
2184 uint8_t otg_inst;
2185 /**
2186 * DIG FE HW instance.
2187 */
2188 uint8_t digfe_inst;
2189 /**
2190 * DIG BE HW instance.
2191 */
2192 uint8_t digbe_inst;
2193 /**
2194 * DP PHY HW instance.
2195 */
2196 uint8_t dpphy_inst;
2197 /**
2198 * AUX HW instance.
2199 */
2200 uint8_t aux_inst;
2201 /**
2202 * Determines if SMU optimzations are enabled/disabled.
2203 */
2204 uint8_t smu_optimizations_en;
2205 /**
2206 * Unused.
2207 * TODO: Remove.
2208 */
2209 uint8_t frame_delay;
2210 /**
2211 * If RFB setup time is greater than the total VBLANK time,
2212 * it is not possible for the sink to capture the video frame
2213 * in the same frame the SDP is sent. In this case,
2214 * the frame capture indication bit should be set and an extra
2215 * static frame should be transmitted to the sink.
2216 */
2217 uint8_t frame_cap_ind;
2218 /**
2219 * Granularity of Y offset supported by sink.
2220 */
2221 uint8_t su_y_granularity;
2222 /**
2223 * Indicates whether sink should start capturing
2224 * immediately following active scan line,
2225 * or starting with the 2nd active scan line.
2226 */
2227 uint8_t line_capture_indication;
2228 /**
2229 * Multi-display optimizations are implemented on certain ASICs.
2230 */
2231 uint8_t multi_disp_optimizations_en;
2232 /**
2233 * The last possible line SDP may be transmitted without violating
2234 * the RFB setup time or entering the active video frame.
2235 */
2236 uint16_t init_sdp_deadline;
2237 /**
2238 * @ rate_control_caps : Indicate FreeSync PSR Sink Capabilities
2239 */
2240 uint8_t rate_control_caps ;
2241 /*
2242 * Force PSRSU always doing full frame update
2243 */
2244 uint8_t force_ffu_mode;
2245 /**
2246 * Length of each horizontal line in us.
2247 */
2248 uint32_t line_time_in_us;
2249 /**
2250 * FEC enable status in driver
2251 */
2252 uint8_t fec_enable_status;
2253 /**
2254 * FEC re-enable delay when PSR exit.
2255 * unit is 100us, range form 0~255(0xFF).
2256 */
2257 uint8_t fec_enable_delay_in100us;
2258 /**
2259 * PSR control version.
2260 */
2261 uint8_t cmd_version;
2262 /**
2263 * Panel Instance.
2264 * Panel instance to identify which psr_state to use
2265 * Currently the support is only for 0 or 1
2266 */
2267 uint8_t panel_inst;
2268 /*
2269 * DSC enable status in driver
2270 */
2271 uint8_t dsc_enable_status;
2272 /*
2273 * Use FSM state for PSR power up/down
2274 */
2275 uint8_t use_phy_fsm;
2276 /**
2277 * frame delay for frame re-lock
2278 */
2279 uint8_t relock_delay_frame_cnt;
2280 /**
2281 * Explicit padding to 2 byte boundary.
2282 */
2283 uint8_t pad3;
2284 /**
2285 * DSC Slice height.
2286 */
2287 uint16_t dsc_slice_height;
2288 /**
2289 * Explicit padding to 4 byte boundary.
2290 */
2291 uint16_t pad;
2292 };
2293
2294 /**
2295 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command.
2296 */
2297 struct dmub_rb_cmd_psr_copy_settings {
2298 /**
2299 * Command header.
2300 */
2301 struct dmub_cmd_header header;
2302 /**
2303 * Data passed from driver to FW in a DMUB_CMD__PSR_COPY_SETTINGS command.
2304 */
2305 struct dmub_cmd_psr_copy_settings_data psr_copy_settings_data;
2306 };
2307
2308 /**
2309 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_LEVEL command.
2310 */
2311 struct dmub_cmd_psr_set_level_data {
2312 /**
2313 * 16-bit value dicated by driver that will enable/disable different functionality.
2314 */
2315 uint16_t psr_level;
2316 /**
2317 * PSR control version.
2318 */
2319 uint8_t cmd_version;
2320 /**
2321 * Panel Instance.
2322 * Panel instance to identify which psr_state to use
2323 * Currently the support is only for 0 or 1
2324 */
2325 uint8_t panel_inst;
2326 };
2327
2328 /**
2329 * Definition of a DMUB_CMD__PSR_SET_LEVEL command.
2330 */
2331 struct dmub_rb_cmd_psr_set_level {
2332 /**
2333 * Command header.
2334 */
2335 struct dmub_cmd_header header;
2336 /**
2337 * Definition of a DMUB_CMD__PSR_SET_LEVEL command.
2338 */
2339 struct dmub_cmd_psr_set_level_data psr_set_level_data;
2340 };
2341
2342 struct dmub_rb_cmd_psr_enable_data {
2343 /**
2344 * PSR control version.
2345 */
2346 uint8_t cmd_version;
2347 /**
2348 * Panel Instance.
2349 * Panel instance to identify which psr_state to use
2350 * Currently the support is only for 0 or 1
2351 */
2352 uint8_t panel_inst;
2353 /**
2354 * Phy state to enter.
2355 * Values to use are defined in dmub_phy_fsm_state
2356 */
2357 uint8_t phy_fsm_state;
2358 /**
2359 * Phy rate for DP - RBR/HBR/HBR2/HBR3.
2360 * Set this using enum phy_link_rate.
2361 * This does not support HDMI/DP2 for now.
2362 */
2363 uint8_t phy_rate;
2364 };
2365
2366 /**
2367 * Definition of a DMUB_CMD__PSR_ENABLE command.
2368 * PSR enable/disable is controlled using the sub_type.
2369 */
2370 struct dmub_rb_cmd_psr_enable {
2371 /**
2372 * Command header.
2373 */
2374 struct dmub_cmd_header header;
2375
2376 struct dmub_rb_cmd_psr_enable_data data;
2377 };
2378
2379 /**
2380 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command.
2381 */
2382 struct dmub_cmd_psr_set_version_data {
2383 /**
2384 * PSR version that FW should implement.
2385 */
2386 enum psr_version version;
2387 /**
2388 * PSR control version.
2389 */
2390 uint8_t cmd_version;
2391 /**
2392 * Panel Instance.
2393 * Panel instance to identify which psr_state to use
2394 * Currently the support is only for 0 or 1
2395 */
2396 uint8_t panel_inst;
2397 /**
2398 * Explicit padding to 4 byte boundary.
2399 */
2400 uint8_t pad[2];
2401 };
2402
2403 /**
2404 * Definition of a DMUB_CMD__PSR_SET_VERSION command.
2405 */
2406 struct dmub_rb_cmd_psr_set_version {
2407 /**
2408 * Command header.
2409 */
2410 struct dmub_cmd_header header;
2411 /**
2412 * Data passed from driver to FW in a DMUB_CMD__PSR_SET_VERSION command.
2413 */
2414 struct dmub_cmd_psr_set_version_data psr_set_version_data;
2415 };
2416
2417 struct dmub_cmd_psr_force_static_data {
2418 /**
2419 * PSR control version.
2420 */
2421 uint8_t cmd_version;
2422 /**
2423 * Panel Instance.
2424 * Panel instance to identify which psr_state to use
2425 * Currently the support is only for 0 or 1
2426 */
2427 uint8_t panel_inst;
2428 /**
2429 * Explicit padding to 4 byte boundary.
2430 */
2431 uint8_t pad[2];
2432 };
2433
2434 /**
2435 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command.
2436 */
2437 struct dmub_rb_cmd_psr_force_static {
2438 /**
2439 * Command header.
2440 */
2441 struct dmub_cmd_header header;
2442 /**
2443 * Data passed from driver to FW in a DMUB_CMD__PSR_FORCE_STATIC command.
2444 */
2445 struct dmub_cmd_psr_force_static_data psr_force_static_data;
2446 };
2447
2448 /**
2449 * PSR SU debug flags.
2450 */
2451 union dmub_psr_su_debug_flags {
2452 /**
2453 * PSR SU debug flags.
2454 */
2455 struct {
2456 /**
2457 * Update dirty rect in SW only.
2458 */
2459 uint8_t update_dirty_rect_only : 1;
2460 /**
2461 * Reset the cursor/plane state before processing the call.
2462 */
2463 uint8_t reset_state : 1;
2464 } bitfields;
2465
2466 /**
2467 * Union for debug flags.
2468 */
2469 uint32_t u32All;
2470 };
2471
2472 /**
2473 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command.
2474 * This triggers a selective update for PSR SU.
2475 */
2476 struct dmub_cmd_update_dirty_rect_data {
2477 /**
2478 * Dirty rects from OS.
2479 */
2480 struct dmub_rect src_dirty_rects[DMUB_MAX_DIRTY_RECTS];
2481 /**
2482 * PSR SU debug flags.
2483 */
2484 union dmub_psr_su_debug_flags debug_flags;
2485 /**
2486 * OTG HW instance.
2487 */
2488 uint8_t pipe_idx;
2489 /**
2490 * Number of dirty rects.
2491 */
2492 uint8_t dirty_rect_count;
2493 /**
2494 * PSR control version.
2495 */
2496 uint8_t cmd_version;
2497 /**
2498 * Panel Instance.
2499 * Panel instance to identify which psr_state to use
2500 * Currently the support is only for 0 or 1
2501 */
2502 uint8_t panel_inst;
2503 };
2504
2505 /**
2506 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command.
2507 */
2508 struct dmub_rb_cmd_update_dirty_rect {
2509 /**
2510 * Command header.
2511 */
2512 struct dmub_cmd_header header;
2513 /**
2514 * Data passed from driver to FW in a DMUB_CMD__UPDATE_DIRTY_RECT command.
2515 */
2516 struct dmub_cmd_update_dirty_rect_data update_dirty_rect_data;
2517 };
2518
2519 /**
2520 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command.
2521 */
2522 union dmub_reg_cursor_control_cfg {
2523 struct {
2524 uint32_t cur_enable: 1;
2525 uint32_t reser0: 3;
2526 uint32_t cur_2x_magnify: 1;
2527 uint32_t reser1: 3;
2528 uint32_t mode: 3;
2529 uint32_t reser2: 5;
2530 uint32_t pitch: 2;
2531 uint32_t reser3: 6;
2532 uint32_t line_per_chunk: 5;
2533 uint32_t reser4: 3;
2534 } bits;
2535 uint32_t raw;
2536 };
2537 struct dmub_cursor_position_cache_hubp {
2538 union dmub_reg_cursor_control_cfg cur_ctl;
2539 union dmub_reg_position_cfg {
2540 struct {
2541 uint32_t cur_x_pos: 16;
2542 uint32_t cur_y_pos: 16;
2543 } bits;
2544 uint32_t raw;
2545 } position;
2546 union dmub_reg_hot_spot_cfg {
2547 struct {
2548 uint32_t hot_x: 16;
2549 uint32_t hot_y: 16;
2550 } bits;
2551 uint32_t raw;
2552 } hot_spot;
2553 union dmub_reg_dst_offset_cfg {
2554 struct {
2555 uint32_t dst_x_offset: 13;
2556 uint32_t reserved: 19;
2557 } bits;
2558 uint32_t raw;
2559 } dst_offset;
2560 };
2561
2562 union dmub_reg_cur0_control_cfg {
2563 struct {
2564 uint32_t cur0_enable: 1;
2565 uint32_t expansion_mode: 1;
2566 uint32_t reser0: 1;
2567 uint32_t cur0_rom_en: 1;
2568 uint32_t mode: 3;
2569 uint32_t reserved: 25;
2570 } bits;
2571 uint32_t raw;
2572 };
2573 struct dmub_cursor_position_cache_dpp {
2574 union dmub_reg_cur0_control_cfg cur0_ctl;
2575 };
2576 struct dmub_cursor_position_cfg {
2577 struct dmub_cursor_position_cache_hubp pHubp;
2578 struct dmub_cursor_position_cache_dpp pDpp;
2579 uint8_t pipe_idx;
2580 /*
2581 * Padding is required. To be 4 Bytes Aligned.
2582 */
2583 uint8_t padding[3];
2584 };
2585
2586 struct dmub_cursor_attribute_cache_hubp {
2587 uint32_t SURFACE_ADDR_HIGH;
2588 uint32_t SURFACE_ADDR;
2589 union dmub_reg_cursor_control_cfg cur_ctl;
2590 union dmub_reg_cursor_size_cfg {
2591 struct {
2592 uint32_t width: 16;
2593 uint32_t height: 16;
2594 } bits;
2595 uint32_t raw;
2596 } size;
2597 union dmub_reg_cursor_settings_cfg {
2598 struct {
2599 uint32_t dst_y_offset: 8;
2600 uint32_t chunk_hdl_adjust: 2;
2601 uint32_t reserved: 22;
2602 } bits;
2603 uint32_t raw;
2604 } settings;
2605 };
2606 struct dmub_cursor_attribute_cache_dpp {
2607 union dmub_reg_cur0_control_cfg cur0_ctl;
2608 };
2609 struct dmub_cursor_attributes_cfg {
2610 struct dmub_cursor_attribute_cache_hubp aHubp;
2611 struct dmub_cursor_attribute_cache_dpp aDpp;
2612 };
2613
2614 struct dmub_cmd_update_cursor_payload0 {
2615 /**
2616 * Cursor dirty rects.
2617 */
2618 struct dmub_rect cursor_rect;
2619 /**
2620 * PSR SU debug flags.
2621 */
2622 union dmub_psr_su_debug_flags debug_flags;
2623 /**
2624 * Cursor enable/disable.
2625 */
2626 uint8_t enable;
2627 /**
2628 * OTG HW instance.
2629 */
2630 uint8_t pipe_idx;
2631 /**
2632 * PSR control version.
2633 */
2634 uint8_t cmd_version;
2635 /**
2636 * Panel Instance.
2637 * Panel instance to identify which psr_state to use
2638 * Currently the support is only for 0 or 1
2639 */
2640 uint8_t panel_inst;
2641 /**
2642 * Cursor Position Register.
2643 * Registers contains Hubp & Dpp modules
2644 */
2645 struct dmub_cursor_position_cfg position_cfg;
2646 };
2647
2648 struct dmub_cmd_update_cursor_payload1 {
2649 struct dmub_cursor_attributes_cfg attribute_cfg;
2650 };
2651
2652 union dmub_cmd_update_cursor_info_data {
2653 struct dmub_cmd_update_cursor_payload0 payload0;
2654 struct dmub_cmd_update_cursor_payload1 payload1;
2655 };
2656 /**
2657 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command.
2658 */
2659 struct dmub_rb_cmd_update_cursor_info {
2660 /**
2661 * Command header.
2662 */
2663 struct dmub_cmd_header header;
2664 /**
2665 * Data passed from driver to FW in a DMUB_CMD__UPDATE_CURSOR_INFO command.
2666 */
2667 union dmub_cmd_update_cursor_info_data update_cursor_info_data;
2668 };
2669
2670 /**
2671 * Data passed from driver to FW in a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
2672 */
2673 struct dmub_cmd_psr_set_vtotal_data {
2674 /**
2675 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when screen idle..
2676 */
2677 uint16_t psr_vtotal_idle;
2678 /**
2679 * PSR control version.
2680 */
2681 uint8_t cmd_version;
2682 /**
2683 * Panel Instance.
2684 * Panel instance to identify which psr_state to use
2685 * Currently the support is only for 0 or 1
2686 */
2687 uint8_t panel_inst;
2688 /*
2689 * 16-bit value dicated by driver that indicates the vtotal in PSR active requirement when doing SU/FFU.
2690 */
2691 uint16_t psr_vtotal_su;
2692 /**
2693 * Explicit padding to 4 byte boundary.
2694 */
2695 uint8_t pad2[2];
2696 };
2697
2698 /**
2699 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
2700 */
2701 struct dmub_rb_cmd_psr_set_vtotal {
2702 /**
2703 * Command header.
2704 */
2705 struct dmub_cmd_header header;
2706 /**
2707 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
2708 */
2709 struct dmub_cmd_psr_set_vtotal_data psr_set_vtotal_data;
2710 };
2711
2712 /**
2713 * Data passed from driver to FW in a DMUB_CMD__SET_PSR_POWER_OPT command.
2714 */
2715 struct dmub_cmd_psr_set_power_opt_data {
2716 /**
2717 * PSR control version.
2718 */
2719 uint8_t cmd_version;
2720 /**
2721 * Panel Instance.
2722 * Panel instance to identify which psr_state to use
2723 * Currently the support is only for 0 or 1
2724 */
2725 uint8_t panel_inst;
2726 /**
2727 * Explicit padding to 4 byte boundary.
2728 */
2729 uint8_t pad[2];
2730 /**
2731 * PSR power option
2732 */
2733 uint32_t power_opt;
2734 };
2735
2736 #define REPLAY_RESIDENCY_MODE_SHIFT (0)
2737 #define REPLAY_RESIDENCY_ENABLE_SHIFT (1)
2738
2739 #define REPLAY_RESIDENCY_MODE_MASK (0x1 << REPLAY_RESIDENCY_MODE_SHIFT)
2740 # define REPLAY_RESIDENCY_MODE_PHY (0x0 << REPLAY_RESIDENCY_MODE_SHIFT)
2741 # define REPLAY_RESIDENCY_MODE_ALPM (0x1 << REPLAY_RESIDENCY_MODE_SHIFT)
2742
2743 #define REPLAY_RESIDENCY_ENABLE_MASK (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT)
2744 # define REPLAY_RESIDENCY_DISABLE (0x0 << REPLAY_RESIDENCY_ENABLE_SHIFT)
2745 # define REPLAY_RESIDENCY_ENABLE (0x1 << REPLAY_RESIDENCY_ENABLE_SHIFT)
2746
2747 enum replay_state {
2748 REPLAY_STATE_0 = 0x0,
2749 REPLAY_STATE_1 = 0x10,
2750 REPLAY_STATE_1A = 0x11,
2751 REPLAY_STATE_2 = 0x20,
2752 REPLAY_STATE_3 = 0x30,
2753 REPLAY_STATE_3INIT = 0x31,
2754 REPLAY_STATE_4 = 0x40,
2755 REPLAY_STATE_4A = 0x41,
2756 REPLAY_STATE_4B = 0x42,
2757 REPLAY_STATE_4C = 0x43,
2758 REPLAY_STATE_4D = 0x44,
2759 REPLAY_STATE_4B_LOCKED = 0x4A,
2760 REPLAY_STATE_4C_UNLOCKED = 0x4B,
2761 REPLAY_STATE_5 = 0x50,
2762 REPLAY_STATE_5A = 0x51,
2763 REPLAY_STATE_5B = 0x52,
2764 REPLAY_STATE_5A_LOCKED = 0x5A,
2765 REPLAY_STATE_5B_UNLOCKED = 0x5B,
2766 REPLAY_STATE_6 = 0x60,
2767 REPLAY_STATE_6A = 0x61,
2768 REPLAY_STATE_6B = 0x62,
2769 REPLAY_STATE_INVALID = 0xFF,
2770 };
2771
2772 /**
2773 * Replay command sub-types.
2774 */
2775 enum dmub_cmd_replay_type {
2776 /**
2777 * Copy driver-calculated parameters to REPLAY state.
2778 */
2779 DMUB_CMD__REPLAY_COPY_SETTINGS = 0,
2780 /**
2781 * Enable REPLAY.
2782 */
2783 DMUB_CMD__REPLAY_ENABLE = 1,
2784 /**
2785 * Set Replay power option.
2786 */
2787 DMUB_CMD__SET_REPLAY_POWER_OPT = 2,
2788 /**
2789 * Set coasting vtotal.
2790 */
2791 DMUB_CMD__REPLAY_SET_COASTING_VTOTAL = 3,
2792 };
2793
2794 /**
2795 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command.
2796 */
2797 struct dmub_cmd_replay_copy_settings_data {
2798 /**
2799 * Flags that can be set by driver to change some replay behaviour.
2800 */
2801 union replay_debug_flags debug;
2802
2803 /**
2804 * @flags: Flags used to determine feature functionality.
2805 */
2806 union replay_hw_flags flags;
2807
2808 /**
2809 * DPP HW instance.
2810 */
2811 uint8_t dpp_inst;
2812 /**
2813 * OTG HW instance.
2814 */
2815 uint8_t otg_inst;
2816 /**
2817 * DIG FE HW instance.
2818 */
2819 uint8_t digfe_inst;
2820 /**
2821 * DIG BE HW instance.
2822 */
2823 uint8_t digbe_inst;
2824 /**
2825 * AUX HW instance.
2826 */
2827 uint8_t aux_inst;
2828 /**
2829 * Panel Instance.
2830 * Panel isntance to identify which psr_state to use
2831 * Currently the support is only for 0 or 1
2832 */
2833 uint8_t panel_inst;
2834 /**
2835 * @pixel_deviation_per_line: Indicate the maximum pixel deviation per line compare
2836 * to Source timing when Sink maintains coasting vtotal during the Replay normal sleep mode
2837 */
2838 uint8_t pixel_deviation_per_line;
2839 /**
2840 * @max_deviation_line: The max number of deviation line that can keep the timing
2841 * synchronized between the Source and Sink during Replay normal sleep mode.
2842 */
2843 uint8_t max_deviation_line;
2844 /**
2845 * Length of each horizontal line in ns.
2846 */
2847 uint32_t line_time_in_ns;
2848 /**
2849 * PHY instance.
2850 */
2851 uint8_t dpphy_inst;
2852 /**
2853 * Determines if SMU optimzations are enabled/disabled.
2854 */
2855 uint8_t smu_optimizations_en;
2856 /**
2857 * Determines if timing sync are enabled/disabled.
2858 */
2859 uint8_t replay_timing_sync_supported;
2860 /*
2861 * Use FSM state for Replay power up/down
2862 */
2863 uint8_t use_phy_fsm;
2864 };
2865
2866 /**
2867 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command.
2868 */
2869 struct dmub_rb_cmd_replay_copy_settings {
2870 /**
2871 * Command header.
2872 */
2873 struct dmub_cmd_header header;
2874 /**
2875 * Data passed from driver to FW in a DMUB_CMD__REPLAY_COPY_SETTINGS command.
2876 */
2877 struct dmub_cmd_replay_copy_settings_data replay_copy_settings_data;
2878 };
2879
2880 /**
2881 * Replay disable / enable state for dmub_rb_cmd_replay_enable_data.enable
2882 */
2883 enum replay_enable {
2884 /**
2885 * Disable REPLAY.
2886 */
2887 REPLAY_DISABLE = 0,
2888 /**
2889 * Enable REPLAY.
2890 */
2891 REPLAY_ENABLE = 1,
2892 };
2893
2894 /**
2895 * Data passed from driver to FW in a DMUB_CMD__REPLAY_ENABLE command.
2896 */
2897 struct dmub_rb_cmd_replay_enable_data {
2898 /**
2899 * Replay enable or disable.
2900 */
2901 uint8_t enable;
2902 /**
2903 * Panel Instance.
2904 * Panel isntance to identify which replay_state to use
2905 * Currently the support is only for 0 or 1
2906 */
2907 uint8_t panel_inst;
2908 /**
2909 * Phy state to enter.
2910 * Values to use are defined in dmub_phy_fsm_state
2911 */
2912 uint8_t phy_fsm_state;
2913 /**
2914 * Phy rate for DP - RBR/HBR/HBR2/HBR3.
2915 * Set this using enum phy_link_rate.
2916 * This does not support HDMI/DP2 for now.
2917 */
2918 uint8_t phy_rate;
2919 };
2920
2921 /**
2922 * Definition of a DMUB_CMD__REPLAY_ENABLE command.
2923 * Replay enable/disable is controlled using action in data.
2924 */
2925 struct dmub_rb_cmd_replay_enable {
2926 /**
2927 * Command header.
2928 */
2929 struct dmub_cmd_header header;
2930
2931 struct dmub_rb_cmd_replay_enable_data data;
2932 };
2933
2934 /**
2935 * Data passed from driver to FW in a DMUB_CMD__SET_REPLAY_POWER_OPT command.
2936 */
2937 struct dmub_cmd_replay_set_power_opt_data {
2938 /**
2939 * Panel Instance.
2940 * Panel isntance to identify which replay_state to use
2941 * Currently the support is only for 0 or 1
2942 */
2943 uint8_t panel_inst;
2944 /**
2945 * Explicit padding to 4 byte boundary.
2946 */
2947 uint8_t pad[3];
2948 /**
2949 * REPLAY power option
2950 */
2951 uint32_t power_opt;
2952 };
2953
2954 /**
2955 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command.
2956 */
2957 struct dmub_rb_cmd_replay_set_power_opt {
2958 /**
2959 * Command header.
2960 */
2961 struct dmub_cmd_header header;
2962 /**
2963 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command.
2964 */
2965 struct dmub_cmd_replay_set_power_opt_data replay_set_power_opt_data;
2966 };
2967
2968 /**
2969 * Data passed from driver to FW in a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command.
2970 */
2971 struct dmub_cmd_replay_set_coasting_vtotal_data {
2972 /**
2973 * 16-bit value dicated by driver that indicates the coasting vtotal.
2974 */
2975 uint16_t coasting_vtotal;
2976 /**
2977 * REPLAY control version.
2978 */
2979 uint8_t cmd_version;
2980 /**
2981 * Panel Instance.
2982 * Panel isntance to identify which replay_state to use
2983 * Currently the support is only for 0 or 1
2984 */
2985 uint8_t panel_inst;
2986 };
2987
2988 /**
2989 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command.
2990 */
2991 struct dmub_rb_cmd_replay_set_coasting_vtotal {
2992 /**
2993 * Command header.
2994 */
2995 struct dmub_cmd_header header;
2996 /**
2997 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command.
2998 */
2999 struct dmub_cmd_replay_set_coasting_vtotal_data replay_set_coasting_vtotal_data;
3000 };
3001
3002 /**
3003 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command.
3004 */
3005 struct dmub_rb_cmd_psr_set_power_opt {
3006 /**
3007 * Command header.
3008 */
3009 struct dmub_cmd_header header;
3010 /**
3011 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command.
3012 */
3013 struct dmub_cmd_psr_set_power_opt_data psr_set_power_opt_data;
3014 };
3015
3016 /**
3017 * Set of HW components that can be locked.
3018 *
3019 * Note: If updating with more HW components, fields
3020 * in dmub_inbox0_cmd_lock_hw must be updated to match.
3021 */
3022 union dmub_hw_lock_flags {
3023 /**
3024 * Set of HW components that can be locked.
3025 */
3026 struct {
3027 /**
3028 * Lock/unlock OTG master update lock.
3029 */
3030 uint8_t lock_pipe : 1;
3031 /**
3032 * Lock/unlock cursor.
3033 */
3034 uint8_t lock_cursor : 1;
3035 /**
3036 * Lock/unlock global update lock.
3037 */
3038 uint8_t lock_dig : 1;
3039 /**
3040 * Triple buffer lock requires additional hw programming to usual OTG master lock.
3041 */
3042 uint8_t triple_buffer_lock : 1;
3043 } bits;
3044
3045 /**
3046 * Union for HW Lock flags.
3047 */
3048 uint8_t u8All;
3049 };
3050
3051 /**
3052 * Instances of HW to be locked.
3053 *
3054 * Note: If updating with more HW components, fields
3055 * in dmub_inbox0_cmd_lock_hw must be updated to match.
3056 */
3057 struct dmub_hw_lock_inst_flags {
3058 /**
3059 * OTG HW instance for OTG master update lock.
3060 */
3061 uint8_t otg_inst;
3062 /**
3063 * OPP instance for cursor lock.
3064 */
3065 uint8_t opp_inst;
3066 /**
3067 * OTG HW instance for global update lock.
3068 * TODO: Remove, and re-use otg_inst.
3069 */
3070 uint8_t dig_inst;
3071 /**
3072 * Explicit pad to 4 byte boundary.
3073 */
3074 uint8_t pad;
3075 };
3076
3077 /**
3078 * Clients that can acquire the HW Lock Manager.
3079 *
3080 * Note: If updating with more clients, fields in
3081 * dmub_inbox0_cmd_lock_hw must be updated to match.
3082 */
3083 enum hw_lock_client {
3084 /**
3085 * Driver is the client of HW Lock Manager.
3086 */
3087 HW_LOCK_CLIENT_DRIVER = 0,
3088 /**
3089 * PSR SU is the client of HW Lock Manager.
3090 */
3091 HW_LOCK_CLIENT_PSR_SU = 1,
3092 /**
3093 * Replay is the client of HW Lock Manager.
3094 */
3095 HW_LOCK_CLIENT_REPLAY = 4,
3096 /**
3097 * Invalid client.
3098 */
3099 HW_LOCK_CLIENT_INVALID = 0xFFFFFFFF,
3100 };
3101
3102 /**
3103 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command.
3104 */
3105 struct dmub_cmd_lock_hw_data {
3106 /**
3107 * Specifies the client accessing HW Lock Manager.
3108 */
3109 enum hw_lock_client client;
3110 /**
3111 * HW instances to be locked.
3112 */
3113 struct dmub_hw_lock_inst_flags inst_flags;
3114 /**
3115 * Which components to be locked.
3116 */
3117 union dmub_hw_lock_flags hw_locks;
3118 /**
3119 * Specifies lock/unlock.
3120 */
3121 uint8_t lock;
3122 /**
3123 * HW can be unlocked separately from releasing the HW Lock Mgr.
3124 * This flag is set if the client wishes to release the object.
3125 */
3126 uint8_t should_release;
3127 /**
3128 * Explicit padding to 4 byte boundary.
3129 */
3130 uint8_t pad;
3131 };
3132
3133 /**
3134 * Definition of a DMUB_CMD__HW_LOCK command.
3135 * Command is used by driver and FW.
3136 */
3137 struct dmub_rb_cmd_lock_hw {
3138 /**
3139 * Command header.
3140 */
3141 struct dmub_cmd_header header;
3142 /**
3143 * Data passed to HW Lock Mgr in a DMUB_CMD__HW_LOCK command.
3144 */
3145 struct dmub_cmd_lock_hw_data lock_hw_data;
3146 };
3147
3148 /**
3149 * ABM command sub-types.
3150 */
3151 enum dmub_cmd_abm_type {
3152 /**
3153 * Initialize parameters for ABM algorithm.
3154 * Data is passed through an indirect buffer.
3155 */
3156 DMUB_CMD__ABM_INIT_CONFIG = 0,
3157 /**
3158 * Set OTG and panel HW instance.
3159 */
3160 DMUB_CMD__ABM_SET_PIPE = 1,
3161 /**
3162 * Set user requested backklight level.
3163 */
3164 DMUB_CMD__ABM_SET_BACKLIGHT = 2,
3165 /**
3166 * Set ABM operating/aggression level.
3167 */
3168 DMUB_CMD__ABM_SET_LEVEL = 3,
3169 /**
3170 * Set ambient light level.
3171 */
3172 DMUB_CMD__ABM_SET_AMBIENT_LEVEL = 4,
3173 /**
3174 * Enable/disable fractional duty cycle for backlight PWM.
3175 */
3176 DMUB_CMD__ABM_SET_PWM_FRAC = 5,
3177
3178 /**
3179 * unregister vertical interrupt after steady state is reached
3180 */
3181 DMUB_CMD__ABM_PAUSE = 6,
3182
3183 /**
3184 * Save and Restore ABM state. On save we save parameters, and
3185 * on restore we update state with passed in data.
3186 */
3187 DMUB_CMD__ABM_SAVE_RESTORE = 7,
3188 };
3189
3190 /**
3191 * Parameters for ABM2.4 algorithm. Passed from driver to FW via an indirect buffer.
3192 * Requirements:
3193 * - Padded explicitly to 32-bit boundary.
3194 * - Must ensure this structure matches the one on driver-side,
3195 * otherwise it won't be aligned.
3196 */
3197 struct abm_config_table {
3198 /**
3199 * Gamma curve thresholds, used for crgb conversion.
3200 */
3201 uint16_t crgb_thresh[NUM_POWER_FN_SEGS]; // 0B
3202 /**
3203 * Gamma curve offsets, used for crgb conversion.
3204 */
3205 uint16_t crgb_offset[NUM_POWER_FN_SEGS]; // 16B
3206 /**
3207 * Gamma curve slopes, used for crgb conversion.
3208 */
3209 uint16_t crgb_slope[NUM_POWER_FN_SEGS]; // 32B
3210 /**
3211 * Custom backlight curve thresholds.
3212 */
3213 uint16_t backlight_thresholds[NUM_BL_CURVE_SEGS]; // 48B
3214 /**
3215 * Custom backlight curve offsets.
3216 */
3217 uint16_t backlight_offsets[NUM_BL_CURVE_SEGS]; // 78B
3218 /**
3219 * Ambient light thresholds.
3220 */
3221 uint16_t ambient_thresholds_lux[NUM_AMBI_LEVEL]; // 112B
3222 /**
3223 * Minimum programmable backlight.
3224 */
3225 uint16_t min_abm_backlight; // 122B
3226 /**
3227 * Minimum reduction values.
3228 */
3229 uint8_t min_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 124B
3230 /**
3231 * Maximum reduction values.
3232 */
3233 uint8_t max_reduction[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 144B
3234 /**
3235 * Bright positive gain.
3236 */
3237 uint8_t bright_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 164B
3238 /**
3239 * Dark negative gain.
3240 */
3241 uint8_t dark_pos_gain[NUM_AMBI_LEVEL][NUM_AGGR_LEVEL]; // 184B
3242 /**
3243 * Hybrid factor.
3244 */
3245 uint8_t hybrid_factor[NUM_AGGR_LEVEL]; // 204B
3246 /**
3247 * Contrast factor.
3248 */
3249 uint8_t contrast_factor[NUM_AGGR_LEVEL]; // 208B
3250 /**
3251 * Deviation gain.
3252 */
3253 uint8_t deviation_gain[NUM_AGGR_LEVEL]; // 212B
3254 /**
3255 * Minimum knee.
3256 */
3257 uint8_t min_knee[NUM_AGGR_LEVEL]; // 216B
3258 /**
3259 * Maximum knee.
3260 */
3261 uint8_t max_knee[NUM_AGGR_LEVEL]; // 220B
3262 /**
3263 * Unused.
3264 */
3265 uint8_t iir_curve[NUM_AMBI_LEVEL]; // 224B
3266 /**
3267 * Explicit padding to 4 byte boundary.
3268 */
3269 uint8_t pad3[3]; // 229B
3270 /**
3271 * Backlight ramp reduction.
3272 */
3273 uint16_t blRampReduction[NUM_AGGR_LEVEL]; // 232B
3274 /**
3275 * Backlight ramp start.
3276 */
3277 uint16_t blRampStart[NUM_AGGR_LEVEL]; // 240B
3278 };
3279
3280 /**
3281 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command.
3282 */
3283 struct dmub_cmd_abm_set_pipe_data {
3284 /**
3285 * OTG HW instance.
3286 */
3287 uint8_t otg_inst;
3288
3289 /**
3290 * Panel Control HW instance.
3291 */
3292 uint8_t panel_inst;
3293
3294 /**
3295 * Controls how ABM will interpret a set pipe or set level command.
3296 */
3297 uint8_t set_pipe_option;
3298
3299 /**
3300 * Unused.
3301 * TODO: Remove.
3302 */
3303 uint8_t ramping_boundary;
3304 };
3305
3306 /**
3307 * Definition of a DMUB_CMD__ABM_SET_PIPE command.
3308 */
3309 struct dmub_rb_cmd_abm_set_pipe {
3310 /**
3311 * Command header.
3312 */
3313 struct dmub_cmd_header header;
3314
3315 /**
3316 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PIPE command.
3317 */
3318 struct dmub_cmd_abm_set_pipe_data abm_set_pipe_data;
3319 };
3320
3321 /**
3322 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command.
3323 */
3324 struct dmub_cmd_abm_set_backlight_data {
3325 /**
3326 * Number of frames to ramp to backlight user level.
3327 */
3328 uint32_t frame_ramp;
3329
3330 /**
3331 * Requested backlight level from user.
3332 */
3333 uint32_t backlight_user_level;
3334
3335 /**
3336 * ABM control version.
3337 */
3338 uint8_t version;
3339
3340 /**
3341 * Panel Control HW instance mask.
3342 * Bit 0 is Panel Control HW instance 0.
3343 * Bit 1 is Panel Control HW instance 1.
3344 */
3345 uint8_t panel_mask;
3346
3347 /**
3348 * Explicit padding to 4 byte boundary.
3349 */
3350 uint8_t pad[2];
3351 };
3352
3353 /**
3354 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command.
3355 */
3356 struct dmub_rb_cmd_abm_set_backlight {
3357 /**
3358 * Command header.
3359 */
3360 struct dmub_cmd_header header;
3361
3362 /**
3363 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_BACKLIGHT command.
3364 */
3365 struct dmub_cmd_abm_set_backlight_data abm_set_backlight_data;
3366 };
3367
3368 /**
3369 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command.
3370 */
3371 struct dmub_cmd_abm_set_level_data {
3372 /**
3373 * Set current ABM operating/aggression level.
3374 */
3375 uint32_t level;
3376
3377 /**
3378 * ABM control version.
3379 */
3380 uint8_t version;
3381
3382 /**
3383 * Panel Control HW instance mask.
3384 * Bit 0 is Panel Control HW instance 0.
3385 * Bit 1 is Panel Control HW instance 1.
3386 */
3387 uint8_t panel_mask;
3388
3389 /**
3390 * Explicit padding to 4 byte boundary.
3391 */
3392 uint8_t pad[2];
3393 };
3394
3395 /**
3396 * Definition of a DMUB_CMD__ABM_SET_LEVEL command.
3397 */
3398 struct dmub_rb_cmd_abm_set_level {
3399 /**
3400 * Command header.
3401 */
3402 struct dmub_cmd_header header;
3403
3404 /**
3405 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_LEVEL command.
3406 */
3407 struct dmub_cmd_abm_set_level_data abm_set_level_data;
3408 };
3409
3410 /**
3411 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
3412 */
3413 struct dmub_cmd_abm_set_ambient_level_data {
3414 /**
3415 * Ambient light sensor reading from OS.
3416 */
3417 uint32_t ambient_lux;
3418
3419 /**
3420 * ABM control version.
3421 */
3422 uint8_t version;
3423
3424 /**
3425 * Panel Control HW instance mask.
3426 * Bit 0 is Panel Control HW instance 0.
3427 * Bit 1 is Panel Control HW instance 1.
3428 */
3429 uint8_t panel_mask;
3430
3431 /**
3432 * Explicit padding to 4 byte boundary.
3433 */
3434 uint8_t pad[2];
3435 };
3436
3437 /**
3438 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
3439 */
3440 struct dmub_rb_cmd_abm_set_ambient_level {
3441 /**
3442 * Command header.
3443 */
3444 struct dmub_cmd_header header;
3445
3446 /**
3447 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
3448 */
3449 struct dmub_cmd_abm_set_ambient_level_data abm_set_ambient_level_data;
3450 };
3451
3452 /**
3453 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command.
3454 */
3455 struct dmub_cmd_abm_set_pwm_frac_data {
3456 /**
3457 * Enable/disable fractional duty cycle for backlight PWM.
3458 * TODO: Convert to uint8_t.
3459 */
3460 uint32_t fractional_pwm;
3461
3462 /**
3463 * ABM control version.
3464 */
3465 uint8_t version;
3466
3467 /**
3468 * Panel Control HW instance mask.
3469 * Bit 0 is Panel Control HW instance 0.
3470 * Bit 1 is Panel Control HW instance 1.
3471 */
3472 uint8_t panel_mask;
3473
3474 /**
3475 * Explicit padding to 4 byte boundary.
3476 */
3477 uint8_t pad[2];
3478 };
3479
3480 /**
3481 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command.
3482 */
3483 struct dmub_rb_cmd_abm_set_pwm_frac {
3484 /**
3485 * Command header.
3486 */
3487 struct dmub_cmd_header header;
3488
3489 /**
3490 * Data passed from driver to FW in a DMUB_CMD__ABM_SET_PWM_FRAC command.
3491 */
3492 struct dmub_cmd_abm_set_pwm_frac_data abm_set_pwm_frac_data;
3493 };
3494
3495 /**
3496 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command.
3497 */
3498 struct dmub_cmd_abm_init_config_data {
3499 /**
3500 * Location of indirect buffer used to pass init data to ABM.
3501 */
3502 union dmub_addr src;
3503
3504 /**
3505 * Indirect buffer length.
3506 */
3507 uint16_t bytes;
3508
3509
3510 /**
3511 * ABM control version.
3512 */
3513 uint8_t version;
3514
3515 /**
3516 * Panel Control HW instance mask.
3517 * Bit 0 is Panel Control HW instance 0.
3518 * Bit 1 is Panel Control HW instance 1.
3519 */
3520 uint8_t panel_mask;
3521
3522 /**
3523 * Explicit padding to 4 byte boundary.
3524 */
3525 uint8_t pad[2];
3526 };
3527
3528 /**
3529 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command.
3530 */
3531 struct dmub_rb_cmd_abm_init_config {
3532 /**
3533 * Command header.
3534 */
3535 struct dmub_cmd_header header;
3536
3537 /**
3538 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command.
3539 */
3540 struct dmub_cmd_abm_init_config_data abm_init_config_data;
3541 };
3542
3543 /**
3544 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command.
3545 */
3546
3547 struct dmub_cmd_abm_pause_data {
3548
3549 /**
3550 * Panel Control HW instance mask.
3551 * Bit 0 is Panel Control HW instance 0.
3552 * Bit 1 is Panel Control HW instance 1.
3553 */
3554 uint8_t panel_mask;
3555
3556 /**
3557 * OTG hw instance
3558 */
3559 uint8_t otg_inst;
3560
3561 /**
3562 * Enable or disable ABM pause
3563 */
3564 uint8_t enable;
3565
3566 /**
3567 * Explicit padding to 4 byte boundary.
3568 */
3569 uint8_t pad[1];
3570 };
3571
3572
3573 /**
3574 * Definition of a DMUB_CMD__ABM_PAUSE command.
3575 */
3576 struct dmub_rb_cmd_abm_pause {
3577 /**
3578 * Command header.
3579 */
3580 struct dmub_cmd_header header;
3581
3582 /**
3583 * Data passed from driver to FW in a DMUB_CMD__ABM_PAUSE command.
3584 */
3585 struct dmub_cmd_abm_pause_data abm_pause_data;
3586 };
3587
3588 /**
3589 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command.
3590 */
3591 struct dmub_rb_cmd_abm_save_restore {
3592 /**
3593 * Command header.
3594 */
3595 struct dmub_cmd_header header;
3596
3597 /**
3598 * OTG hw instance
3599 */
3600 uint8_t otg_inst;
3601
3602 /**
3603 * Enable or disable ABM pause
3604 */
3605 uint8_t freeze;
3606
3607 /**
3608 * Explicit padding to 4 byte boundary.
3609 */
3610 uint8_t debug;
3611
3612 /**
3613 * Data passed from driver to FW in a DMUB_CMD__ABM_INIT_CONFIG command.
3614 */
3615 struct dmub_cmd_abm_init_config_data abm_init_config_data;
3616 };
3617
3618 /**
3619 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command.
3620 */
3621 struct dmub_cmd_query_feature_caps_data {
3622 /**
3623 * DMUB feature capabilities.
3624 * After DMUB init, driver will query FW capabilities prior to enabling certain features.
3625 */
3626 struct dmub_feature_caps feature_caps;
3627 };
3628
3629 /**
3630 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command.
3631 */
3632 struct dmub_rb_cmd_query_feature_caps {
3633 /**
3634 * Command header.
3635 */
3636 struct dmub_cmd_header header;
3637 /**
3638 * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command.
3639 */
3640 struct dmub_cmd_query_feature_caps_data query_feature_caps_data;
3641 };
3642
3643 /**
3644 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
3645 */
3646 struct dmub_cmd_visual_confirm_color_data {
3647 /**
3648 * DMUB feature capabilities.
3649 * After DMUB init, driver will query FW capabilities prior to enabling certain features.
3650 */
3651 struct dmub_visual_confirm_color visual_confirm_color;
3652 };
3653
3654 /**
3655 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
3656 */
3657 struct dmub_rb_cmd_get_visual_confirm_color {
3658 /**
3659 * Command header.
3660 */
3661 struct dmub_cmd_header header;
3662 /**
3663 * Data passed from driver to FW in a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
3664 */
3665 struct dmub_cmd_visual_confirm_color_data visual_confirm_color_data;
3666 };
3667
3668 struct dmub_optc_state {
3669 uint32_t v_total_max;
3670 uint32_t v_total_min;
3671 uint32_t tg_inst;
3672 };
3673
3674 struct dmub_rb_cmd_drr_update {
3675 struct dmub_cmd_header header;
3676 struct dmub_optc_state dmub_optc_state_req;
3677 };
3678
3679 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data {
3680 uint32_t pix_clk_100hz;
3681 uint8_t max_ramp_step;
3682 uint8_t pipes;
3683 uint8_t min_refresh_in_hz;
3684 uint8_t pipe_count;
3685 uint8_t pipe_index[4];
3686 };
3687
3688 struct dmub_cmd_fw_assisted_mclk_switch_config {
3689 uint8_t fams_enabled;
3690 uint8_t visual_confirm_enabled;
3691 uint16_t vactive_stretch_margin_us; // Extra vblank stretch required when doing FPO + Vactive
3692 struct dmub_cmd_fw_assisted_mclk_switch_pipe_data pipe_data[DMUB_MAX_FPO_STREAMS];
3693 };
3694
3695 struct dmub_rb_cmd_fw_assisted_mclk_switch {
3696 struct dmub_cmd_header header;
3697 struct dmub_cmd_fw_assisted_mclk_switch_config config_data;
3698 };
3699
3700 /**
3701 * enum dmub_cmd_panel_cntl_type - Panel control command.
3702 */
3703 enum dmub_cmd_panel_cntl_type {
3704 /**
3705 * Initializes embedded panel hardware blocks.
3706 */
3707 DMUB_CMD__PANEL_CNTL_HW_INIT = 0,
3708 /**
3709 * Queries backlight info for the embedded panel.
3710 */
3711 DMUB_CMD__PANEL_CNTL_QUERY_BACKLIGHT_INFO = 1,
3712 };
3713
3714 /**
3715 * struct dmub_cmd_panel_cntl_data - Panel control data.
3716 */
3717 struct dmub_cmd_panel_cntl_data {
3718 uint32_t inst; /**< panel instance */
3719 uint32_t current_backlight; /* in/out */
3720 uint32_t bl_pwm_cntl; /* in/out */
3721 uint32_t bl_pwm_period_cntl; /* in/out */
3722 uint32_t bl_pwm_ref_div1; /* in/out */
3723 uint8_t is_backlight_on : 1; /* in/out */
3724 uint8_t is_powered_on : 1; /* in/out */
3725 uint8_t padding[3];
3726 uint32_t bl_pwm_ref_div2; /* in/out */
3727 uint8_t reserved[4];
3728 };
3729
3730 /**
3731 * struct dmub_rb_cmd_panel_cntl - Panel control command.
3732 */
3733 struct dmub_rb_cmd_panel_cntl {
3734 struct dmub_cmd_header header; /**< header */
3735 struct dmub_cmd_panel_cntl_data data; /**< payload */
3736 };
3737
3738 /**
3739 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
3740 */
3741 struct dmub_cmd_lvtma_control_data {
3742 uint8_t uc_pwr_action; /**< LVTMA_ACTION */
3743 uint8_t bypass_panel_control_wait;
3744 uint8_t reserved_0[2]; /**< For future use */
3745 uint8_t panel_inst; /**< LVTMA control instance */
3746 uint8_t reserved_1[3]; /**< For future use */
3747 };
3748
3749 /**
3750 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
3751 */
3752 struct dmub_rb_cmd_lvtma_control {
3753 /**
3754 * Command header.
3755 */
3756 struct dmub_cmd_header header;
3757 /**
3758 * Data passed from driver to FW in a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
3759 */
3760 struct dmub_cmd_lvtma_control_data data;
3761 };
3762
3763 /**
3764 * Data passed in/out in a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command.
3765 */
3766 struct dmub_rb_cmd_transmitter_query_dp_alt_data {
3767 uint8_t phy_id; /**< 0=UNIPHYA, 1=UNIPHYB, 2=UNIPHYC, 3=UNIPHYD, 4=UNIPHYE, 5=UNIPHYF */
3768 uint8_t is_usb; /**< is phy is usb */
3769 uint8_t is_dp_alt_disable; /**< is dp alt disable */
3770 uint8_t is_dp4; /**< is dp in 4 lane */
3771 };
3772
3773 /**
3774 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command.
3775 */
3776 struct dmub_rb_cmd_transmitter_query_dp_alt {
3777 struct dmub_cmd_header header; /**< header */
3778 struct dmub_rb_cmd_transmitter_query_dp_alt_data data; /**< payload */
3779 };
3780
3781 /**
3782 * Maximum number of bytes a chunk sent to DMUB for parsing
3783 */
3784 #define DMUB_EDID_CEA_DATA_CHUNK_BYTES 8
3785
3786 /**
3787 * Represent a chunk of CEA blocks sent to DMUB for parsing
3788 */
3789 struct dmub_cmd_send_edid_cea {
3790 uint16_t offset; /**< offset into the CEA block */
3791 uint8_t length; /**< number of bytes in payload to copy as part of CEA block */
3792 uint16_t cea_total_length; /**< total length of the CEA block */
3793 uint8_t payload[DMUB_EDID_CEA_DATA_CHUNK_BYTES]; /**< data chunk of the CEA block */
3794 uint8_t pad[3]; /**< padding and for future expansion */
3795 };
3796
3797 /**
3798 * Result of VSDB parsing from CEA block
3799 */
3800 struct dmub_cmd_edid_cea_amd_vsdb {
3801 uint8_t vsdb_found; /**< 1 if parsing has found valid AMD VSDB */
3802 uint8_t freesync_supported; /**< 1 if Freesync is supported */
3803 uint16_t amd_vsdb_version; /**< AMD VSDB version */
3804 uint16_t min_frame_rate; /**< Maximum frame rate */
3805 uint16_t max_frame_rate; /**< Minimum frame rate */
3806 };
3807
3808 /**
3809 * Result of sending a CEA chunk
3810 */
3811 struct dmub_cmd_edid_cea_ack {
3812 uint16_t offset; /**< offset of the chunk into the CEA block */
3813 uint8_t success; /**< 1 if this sending of chunk succeeded */
3814 uint8_t pad; /**< padding and for future expansion */
3815 };
3816
3817 /**
3818 * Specify whether the result is an ACK/NACK or the parsing has finished
3819 */
3820 enum dmub_cmd_edid_cea_reply_type {
3821 DMUB_CMD__EDID_CEA_AMD_VSDB = 1, /**< VSDB parsing has finished */
3822 DMUB_CMD__EDID_CEA_ACK = 2, /**< acknowledges the CEA sending is OK or failing */
3823 };
3824
3825 /**
3826 * Definition of a DMUB_CMD__EDID_CEA command.
3827 */
3828 struct dmub_rb_cmd_edid_cea {
3829 struct dmub_cmd_header header; /**< Command header */
3830 union dmub_cmd_edid_cea_data {
3831 struct dmub_cmd_send_edid_cea input; /**< input to send CEA chunks */
3832 struct dmub_cmd_edid_cea_output { /**< output with results */
3833 uint8_t type; /**< dmub_cmd_edid_cea_reply_type */
3834 union {
3835 struct dmub_cmd_edid_cea_amd_vsdb amd_vsdb;
3836 struct dmub_cmd_edid_cea_ack ack;
3837 };
3838 } output; /**< output to retrieve ACK/NACK or VSDB parsing results */
3839 } data; /**< Command data */
3840
3841 };
3842
3843 /**
3844 * struct dmub_cmd_cable_id_input - Defines the input of DMUB_CMD_GET_USBC_CABLE_ID command.
3845 */
3846 struct dmub_cmd_cable_id_input {
3847 uint8_t phy_inst; /**< phy inst for cable id data */
3848 };
3849
3850 /**
3851 * struct dmub_cmd_cable_id_input - Defines the output of DMUB_CMD_GET_USBC_CABLE_ID command.
3852 */
3853 struct dmub_cmd_cable_id_output {
3854 uint8_t UHBR10_20_CAPABILITY :2; /**< b'01 for UHBR10 support, b'10 for both UHBR10 and UHBR20 support */
3855 uint8_t UHBR13_5_CAPABILITY :1; /**< b'1 for UHBR13.5 support */
3856 uint8_t CABLE_TYPE :3; /**< b'01 for passive cable, b'10 for active LRD cable, b'11 for active retimer cable */
3857 uint8_t RESERVED :2; /**< reserved means not defined */
3858 };
3859
3860 /**
3861 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command
3862 */
3863 struct dmub_rb_cmd_get_usbc_cable_id {
3864 struct dmub_cmd_header header; /**< Command header */
3865 /**
3866 * Data passed from driver to FW in a DMUB_CMD_GET_USBC_CABLE_ID command.
3867 */
3868 union dmub_cmd_cable_id_data {
3869 struct dmub_cmd_cable_id_input input; /**< Input */
3870 struct dmub_cmd_cable_id_output output; /**< Output */
3871 uint8_t output_raw; /**< Raw data output */
3872 } data;
3873 };
3874
3875 /**
3876 * Command type of a DMUB_CMD__SECURE_DISPLAY command
3877 */
3878 enum dmub_cmd_secure_display_type {
3879 DMUB_CMD__SECURE_DISPLAY_TEST_CMD = 0, /* test command to only check if inbox message works */
3880 DMUB_CMD__SECURE_DISPLAY_CRC_STOP_UPDATE,
3881 DMUB_CMD__SECURE_DISPLAY_CRC_WIN_NOTIFY
3882 };
3883
3884 /**
3885 * Definition of a DMUB_CMD__SECURE_DISPLAY command
3886 */
3887 struct dmub_rb_cmd_secure_display {
3888 struct dmub_cmd_header header;
3889 /**
3890 * Data passed from driver to dmub firmware.
3891 */
3892 struct dmub_cmd_roi_info {
3893 uint16_t x_start;
3894 uint16_t x_end;
3895 uint16_t y_start;
3896 uint16_t y_end;
3897 uint8_t otg_id;
3898 uint8_t phy_id;
3899 } roi_info;
3900 };
3901
3902 /**
3903 * union dmub_rb_cmd - DMUB inbox command.
3904 */
3905 union dmub_rb_cmd {
3906 /**
3907 * Elements shared with all commands.
3908 */
3909 struct dmub_rb_cmd_common cmd_common;
3910 /**
3911 * Definition of a DMUB_CMD__REG_SEQ_READ_MODIFY_WRITE command.
3912 */
3913 struct dmub_rb_cmd_read_modify_write read_modify_write;
3914 /**
3915 * Definition of a DMUB_CMD__REG_SEQ_FIELD_UPDATE_SEQ command.
3916 */
3917 struct dmub_rb_cmd_reg_field_update_sequence reg_field_update_seq;
3918 /**
3919 * Definition of a DMUB_CMD__REG_SEQ_BURST_WRITE command.
3920 */
3921 struct dmub_rb_cmd_burst_write burst_write;
3922 /**
3923 * Definition of a DMUB_CMD__REG_REG_WAIT command.
3924 */
3925 struct dmub_rb_cmd_reg_wait reg_wait;
3926 /**
3927 * Definition of a DMUB_CMD__VBIOS_DIGX_ENCODER_CONTROL command.
3928 */
3929 struct dmub_rb_cmd_digx_encoder_control digx_encoder_control;
3930 /**
3931 * Definition of a DMUB_CMD__VBIOS_SET_PIXEL_CLOCK command.
3932 */
3933 struct dmub_rb_cmd_set_pixel_clock set_pixel_clock;
3934 /**
3935 * Definition of a DMUB_CMD__VBIOS_ENABLE_DISP_POWER_GATING command.
3936 */
3937 struct dmub_rb_cmd_enable_disp_power_gating enable_disp_power_gating;
3938 /**
3939 * Definition of a DMUB_CMD__VBIOS_DPPHY_INIT command.
3940 */
3941 struct dmub_rb_cmd_dpphy_init dpphy_init;
3942 /**
3943 * Definition of a DMUB_CMD__VBIOS_DIG1_TRANSMITTER_CONTROL command.
3944 */
3945 struct dmub_rb_cmd_dig1_transmitter_control dig1_transmitter_control;
3946 /**
3947 * Definition of a DMUB_CMD__VBIOS_DOMAIN_CONTROL command.
3948 */
3949 struct dmub_rb_cmd_domain_control domain_control;
3950 /**
3951 * Definition of a DMUB_CMD__PSR_SET_VERSION command.
3952 */
3953 struct dmub_rb_cmd_psr_set_version psr_set_version;
3954 /**
3955 * Definition of a DMUB_CMD__PSR_COPY_SETTINGS command.
3956 */
3957 struct dmub_rb_cmd_psr_copy_settings psr_copy_settings;
3958 /**
3959 * Definition of a DMUB_CMD__PSR_ENABLE command.
3960 */
3961 struct dmub_rb_cmd_psr_enable psr_enable;
3962 /**
3963 * Definition of a DMUB_CMD__PSR_SET_LEVEL command.
3964 */
3965 struct dmub_rb_cmd_psr_set_level psr_set_level;
3966 /**
3967 * Definition of a DMUB_CMD__PSR_FORCE_STATIC command.
3968 */
3969 struct dmub_rb_cmd_psr_force_static psr_force_static;
3970 /**
3971 * Definition of a DMUB_CMD__UPDATE_DIRTY_RECT command.
3972 */
3973 struct dmub_rb_cmd_update_dirty_rect update_dirty_rect;
3974 /**
3975 * Definition of a DMUB_CMD__UPDATE_CURSOR_INFO command.
3976 */
3977 struct dmub_rb_cmd_update_cursor_info update_cursor_info;
3978 /**
3979 * Definition of a DMUB_CMD__HW_LOCK command.
3980 * Command is used by driver and FW.
3981 */
3982 struct dmub_rb_cmd_lock_hw lock_hw;
3983 /**
3984 * Definition of a DMUB_CMD__SET_SINK_VTOTAL_IN_PSR_ACTIVE command.
3985 */
3986 struct dmub_rb_cmd_psr_set_vtotal psr_set_vtotal;
3987 /**
3988 * Definition of a DMUB_CMD__SET_PSR_POWER_OPT command.
3989 */
3990 struct dmub_rb_cmd_psr_set_power_opt psr_set_power_opt;
3991 /**
3992 * Definition of a DMUB_CMD__PLAT_54186_WA command.
3993 */
3994 struct dmub_rb_cmd_PLAT_54186_wa PLAT_54186_wa;
3995 /**
3996 * Definition of a DMUB_CMD__MALL command.
3997 */
3998 struct dmub_rb_cmd_mall mall;
3999 /**
4000 * Definition of a DMUB_CMD__CAB command.
4001 */
4002 struct dmub_rb_cmd_cab_for_ss cab;
4003
4004 struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 fw_assisted_mclk_switch_v2;
4005
4006 /**
4007 * Definition of a DMUB_CMD__IDLE_OPT_DCN_RESTORE command.
4008 */
4009 struct dmub_rb_cmd_idle_opt_dcn_restore dcn_restore;
4010
4011 /**
4012 * Definition of a DMUB_CMD__CLK_MGR_NOTIFY_CLOCKS command.
4013 */
4014 struct dmub_rb_cmd_clk_mgr_notify_clocks notify_clocks;
4015
4016 /**
4017 * Definition of DMUB_CMD__PANEL_CNTL commands.
4018 */
4019 struct dmub_rb_cmd_panel_cntl panel_cntl;
4020 /**
4021 * Definition of a DMUB_CMD__ABM_SET_PIPE command.
4022 */
4023 struct dmub_rb_cmd_abm_set_pipe abm_set_pipe;
4024
4025 /**
4026 * Definition of a DMUB_CMD__ABM_SET_BACKLIGHT command.
4027 */
4028 struct dmub_rb_cmd_abm_set_backlight abm_set_backlight;
4029
4030 /**
4031 * Definition of a DMUB_CMD__ABM_SET_LEVEL command.
4032 */
4033 struct dmub_rb_cmd_abm_set_level abm_set_level;
4034
4035 /**
4036 * Definition of a DMUB_CMD__ABM_SET_AMBIENT_LEVEL command.
4037 */
4038 struct dmub_rb_cmd_abm_set_ambient_level abm_set_ambient_level;
4039
4040 /**
4041 * Definition of a DMUB_CMD__ABM_SET_PWM_FRAC command.
4042 */
4043 struct dmub_rb_cmd_abm_set_pwm_frac abm_set_pwm_frac;
4044
4045 /**
4046 * Definition of a DMUB_CMD__ABM_INIT_CONFIG command.
4047 */
4048 struct dmub_rb_cmd_abm_init_config abm_init_config;
4049
4050 /**
4051 * Definition of a DMUB_CMD__ABM_PAUSE command.
4052 */
4053 struct dmub_rb_cmd_abm_pause abm_pause;
4054
4055 /**
4056 * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command.
4057 */
4058 struct dmub_rb_cmd_abm_save_restore abm_save_restore;
4059
4060 /**
4061 * Definition of a DMUB_CMD__DP_AUX_ACCESS command.
4062 */
4063 struct dmub_rb_cmd_dp_aux_access dp_aux_access;
4064
4065 /**
4066 * Definition of a DMUB_CMD__OUTBOX1_ENABLE command.
4067 */
4068 struct dmub_rb_cmd_outbox1_enable outbox1_enable;
4069
4070 /**
4071 * Definition of a DMUB_CMD__QUERY_FEATURE_CAPS command.
4072 */
4073 struct dmub_rb_cmd_query_feature_caps query_feature_caps;
4074
4075 /**
4076 * Definition of a DMUB_CMD__GET_VISUAL_CONFIRM_COLOR command.
4077 */
4078 struct dmub_rb_cmd_get_visual_confirm_color visual_confirm_color;
4079 struct dmub_rb_cmd_drr_update drr_update;
4080 struct dmub_rb_cmd_fw_assisted_mclk_switch fw_assisted_mclk_switch;
4081
4082 /**
4083 * Definition of a DMUB_CMD__VBIOS_LVTMA_CONTROL command.
4084 */
4085 struct dmub_rb_cmd_lvtma_control lvtma_control;
4086 /**
4087 * Definition of a DMUB_CMD__VBIOS_TRANSMITTER_QUERY_DP_ALT command.
4088 */
4089 struct dmub_rb_cmd_transmitter_query_dp_alt query_dp_alt;
4090 /**
4091 * Definition of a DMUB_CMD__DPIA_DIG1_CONTROL command.
4092 */
4093 struct dmub_rb_cmd_dig1_dpia_control dig1_dpia_control;
4094 /**
4095 * Definition of a DMUB_CMD__DPIA_SET_CONFIG_ACCESS command.
4096 */
4097 struct dmub_rb_cmd_set_config_access set_config_access;
4098 /**
4099 * Definition of a DMUB_CMD__DPIA_MST_ALLOC_SLOTS command.
4100 */
4101 struct dmub_rb_cmd_set_mst_alloc_slots set_mst_alloc_slots;
4102 /**
4103 * Definition of a DMUB_CMD__EDID_CEA command.
4104 */
4105 struct dmub_rb_cmd_edid_cea edid_cea;
4106 /**
4107 * Definition of a DMUB_CMD_GET_USBC_CABLE_ID command.
4108 */
4109 struct dmub_rb_cmd_get_usbc_cable_id cable_id;
4110
4111 /**
4112 * Definition of a DMUB_CMD__QUERY_HPD_STATE command.
4113 */
4114 struct dmub_rb_cmd_query_hpd_state query_hpd;
4115 /**
4116 * Definition of a DMUB_CMD__SECURE_DISPLAY command.
4117 */
4118 struct dmub_rb_cmd_secure_display secure_display;
4119
4120 /**
4121 * Definition of a DMUB_CMD__DPIA_HPD_INT_ENABLE command.
4122 */
4123 struct dmub_rb_cmd_dpia_hpd_int_enable dpia_hpd_int_enable;
4124 /**
4125 * Definition of a DMUB_CMD__IDLE_OPT_DCN_NOTIFY_IDLE command.
4126 */
4127 struct dmub_rb_cmd_idle_opt_dcn_notify_idle idle_opt_notify_idle;
4128 /*
4129 * Definition of a DMUB_CMD__REPLAY_COPY_SETTINGS command.
4130 */
4131 struct dmub_rb_cmd_replay_copy_settings replay_copy_settings;
4132 /**
4133 * Definition of a DMUB_CMD__REPLAY_ENABLE command.
4134 */
4135 struct dmub_rb_cmd_replay_enable replay_enable;
4136 /**
4137 * Definition of a DMUB_CMD__SET_REPLAY_POWER_OPT command.
4138 */
4139 struct dmub_rb_cmd_replay_set_power_opt replay_set_power_opt;
4140 /**
4141 * Definition of a DMUB_CMD__REPLAY_SET_COASTING_VTOTAL command.
4142 */
4143 struct dmub_rb_cmd_replay_set_coasting_vtotal replay_set_coasting_vtotal;
4144 };
4145
4146 /**
4147 * union dmub_rb_out_cmd - Outbox command
4148 */
4149 union dmub_rb_out_cmd {
4150 /**
4151 * Parameters common to every command.
4152 */
4153 struct dmub_rb_cmd_common cmd_common;
4154 /**
4155 * AUX reply command.
4156 */
4157 struct dmub_rb_cmd_dp_aux_reply dp_aux_reply;
4158 /**
4159 * HPD notify command.
4160 */
4161 struct dmub_rb_cmd_dp_hpd_notify dp_hpd_notify;
4162 /**
4163 * SET_CONFIG reply command.
4164 */
4165 struct dmub_rb_cmd_dp_set_config_reply set_config_reply;
4166 /**
4167 * DPIA notification command.
4168 */
4169 struct dmub_rb_cmd_dpia_notification dpia_notification;
4170 };
4171 #pragma pack(pop)
4172
4173
4174 //==============================================================================
4175 //</DMUB_CMD>===================================================================
4176 //==============================================================================
4177 //< DMUB_RB>====================================================================
4178 //==============================================================================
4179
4180 #if defined(__cplusplus)
4181 extern "C" {
4182 #endif
4183
4184 /**
4185 * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer
4186 */
4187 struct dmub_rb_init_params {
4188 void *ctx; /**< Caller provided context pointer */
4189 void *base_address; /**< CPU base address for ring's data */
4190 uint32_t capacity; /**< Ringbuffer capacity in bytes */
4191 uint32_t read_ptr; /**< Initial read pointer for consumer in bytes */
4192 uint32_t write_ptr; /**< Initial write pointer for producer in bytes */
4193 };
4194
4195 /**
4196 * struct dmub_rb - Inbox or outbox DMUB ringbuffer
4197 */
4198 struct dmub_rb {
4199 void *base_address; /**< CPU address for the ring's data */
4200 uint32_t rptr; /**< Read pointer for consumer in bytes */
4201 uint32_t wrpt; /**< Write pointer for producer in bytes */
4202 uint32_t capacity; /**< Ringbuffer capacity in bytes */
4203
4204 void *ctx; /**< Caller provided context pointer */
4205 void *dmub; /**< Pointer to the DMUB interface */
4206 };
4207
4208 /**
4209 * @brief Checks if the ringbuffer is empty.
4210 *
4211 * @param rb DMUB Ringbuffer
4212 * @return true if empty
4213 * @return false otherwise
4214 */
dmub_rb_empty(struct dmub_rb * rb)4215 static inline bool dmub_rb_empty(struct dmub_rb *rb)
4216 {
4217 return (rb->wrpt == rb->rptr);
4218 }
4219
4220 /**
4221 * @brief Checks if the ringbuffer is full
4222 *
4223 * @param rb DMUB Ringbuffer
4224 * @return true if full
4225 * @return false otherwise
4226 */
dmub_rb_full(struct dmub_rb * rb)4227 static inline bool dmub_rb_full(struct dmub_rb *rb)
4228 {
4229 uint32_t data_count;
4230
4231 if (rb->wrpt >= rb->rptr)
4232 data_count = rb->wrpt - rb->rptr;
4233 else
4234 data_count = rb->capacity - (rb->rptr - rb->wrpt);
4235
4236 return (data_count == (rb->capacity - DMUB_RB_CMD_SIZE));
4237 }
4238
4239 /**
4240 * @brief Pushes a command into the ringbuffer
4241 *
4242 * @param rb DMUB ringbuffer
4243 * @param cmd The command to push
4244 * @return true if the ringbuffer was not full
4245 * @return false otherwise
4246 */
dmub_rb_push_front(struct dmub_rb * rb,const union dmub_rb_cmd * cmd)4247 static inline bool dmub_rb_push_front(struct dmub_rb *rb,
4248 const union dmub_rb_cmd *cmd)
4249 {
4250 uint64_t volatile *dst = (uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->wrpt);
4251 const uint64_t *src = (const uint64_t *)cmd;
4252 uint8_t i;
4253
4254 if (dmub_rb_full(rb))
4255 return false;
4256
4257 // copying data
4258 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)
4259 *dst++ = *src++;
4260
4261 rb->wrpt += DMUB_RB_CMD_SIZE;
4262
4263 if (rb->wrpt >= rb->capacity)
4264 rb->wrpt %= rb->capacity;
4265
4266 return true;
4267 }
4268
4269 /**
4270 * @brief Pushes a command into the DMUB outbox ringbuffer
4271 *
4272 * @param rb DMUB outbox ringbuffer
4273 * @param cmd Outbox command
4274 * @return true if not full
4275 * @return false otherwise
4276 */
dmub_rb_out_push_front(struct dmub_rb * rb,const union dmub_rb_out_cmd * cmd)4277 static inline bool dmub_rb_out_push_front(struct dmub_rb *rb,
4278 const union dmub_rb_out_cmd *cmd)
4279 {
4280 uint8_t *dst = (uint8_t *)(rb->base_address) + rb->wrpt;
4281 const uint8_t *src = (const uint8_t *)cmd;
4282
4283 if (dmub_rb_full(rb))
4284 return false;
4285
4286 dmub_memcpy(dst, src, DMUB_RB_CMD_SIZE);
4287
4288 rb->wrpt += DMUB_RB_CMD_SIZE;
4289
4290 if (rb->wrpt >= rb->capacity)
4291 rb->wrpt %= rb->capacity;
4292
4293 return true;
4294 }
4295
4296 /**
4297 * @brief Returns the next unprocessed command in the ringbuffer.
4298 *
4299 * @param rb DMUB ringbuffer
4300 * @param cmd The command to return
4301 * @return true if not empty
4302 * @return false otherwise
4303 */
dmub_rb_front(struct dmub_rb * rb,union dmub_rb_cmd ** cmd)4304 static inline bool dmub_rb_front(struct dmub_rb *rb,
4305 union dmub_rb_cmd **cmd)
4306 {
4307 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rb->rptr;
4308
4309 if (dmub_rb_empty(rb))
4310 return false;
4311
4312 *cmd = (union dmub_rb_cmd *)rb_cmd;
4313
4314 return true;
4315 }
4316
4317 /**
4318 * @brief Determines the next ringbuffer offset.
4319 *
4320 * @param rb DMUB inbox ringbuffer
4321 * @param num_cmds Number of commands
4322 * @param next_rptr The next offset in the ringbuffer
4323 */
dmub_rb_get_rptr_with_offset(struct dmub_rb * rb,uint32_t num_cmds,uint32_t * next_rptr)4324 static inline void dmub_rb_get_rptr_with_offset(struct dmub_rb *rb,
4325 uint32_t num_cmds,
4326 uint32_t *next_rptr)
4327 {
4328 *next_rptr = rb->rptr + DMUB_RB_CMD_SIZE * num_cmds;
4329
4330 if (*next_rptr >= rb->capacity)
4331 *next_rptr %= rb->capacity;
4332 }
4333
4334 /**
4335 * @brief Returns a pointer to a command in the inbox.
4336 *
4337 * @param rb DMUB inbox ringbuffer
4338 * @param cmd The inbox command to return
4339 * @param rptr The ringbuffer offset
4340 * @return true if not empty
4341 * @return false otherwise
4342 */
dmub_rb_peek_offset(struct dmub_rb * rb,union dmub_rb_cmd ** cmd,uint32_t rptr)4343 static inline bool dmub_rb_peek_offset(struct dmub_rb *rb,
4344 union dmub_rb_cmd **cmd,
4345 uint32_t rptr)
4346 {
4347 uint8_t *rb_cmd = (uint8_t *)(rb->base_address) + rptr;
4348
4349 if (dmub_rb_empty(rb))
4350 return false;
4351
4352 *cmd = (union dmub_rb_cmd *)rb_cmd;
4353
4354 return true;
4355 }
4356
4357 /**
4358 * @brief Returns the next unprocessed command in the outbox.
4359 *
4360 * @param rb DMUB outbox ringbuffer
4361 * @param cmd The outbox command to return
4362 * @return true if not empty
4363 * @return false otherwise
4364 */
dmub_rb_out_front(struct dmub_rb * rb,union dmub_rb_out_cmd * cmd)4365 static inline bool dmub_rb_out_front(struct dmub_rb *rb,
4366 union dmub_rb_out_cmd *cmd)
4367 {
4368 const uint64_t volatile *src = (const uint64_t volatile *)((uint8_t *)(rb->base_address) + rb->rptr);
4369 uint64_t *dst = (uint64_t *)cmd;
4370 uint8_t i;
4371
4372 if (dmub_rb_empty(rb))
4373 return false;
4374
4375 // copying data
4376 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)
4377 *dst++ = *src++;
4378
4379 return true;
4380 }
4381
4382 /**
4383 * @brief Removes the front entry in the ringbuffer.
4384 *
4385 * @param rb DMUB ringbuffer
4386 * @return true if the command was removed
4387 * @return false if there were no commands
4388 */
dmub_rb_pop_front(struct dmub_rb * rb)4389 static inline bool dmub_rb_pop_front(struct dmub_rb *rb)
4390 {
4391 if (dmub_rb_empty(rb))
4392 return false;
4393
4394 rb->rptr += DMUB_RB_CMD_SIZE;
4395
4396 if (rb->rptr >= rb->capacity)
4397 rb->rptr %= rb->capacity;
4398
4399 return true;
4400 }
4401
4402 /**
4403 * @brief Flushes commands in the ringbuffer to framebuffer memory.
4404 *
4405 * Avoids a race condition where DMCUB accesses memory while
4406 * there are still writes in flight to framebuffer.
4407 *
4408 * @param rb DMUB ringbuffer
4409 */
dmub_rb_flush_pending(const struct dmub_rb * rb)4410 static inline void dmub_rb_flush_pending(const struct dmub_rb *rb)
4411 {
4412 uint32_t rptr = rb->rptr;
4413 uint32_t wptr = rb->wrpt;
4414
4415 while (rptr != wptr) {
4416 uint64_t *data = (uint64_t *)((uint8_t *)(rb->base_address) + rptr);
4417 uint8_t i;
4418
4419 /* Don't remove this.
4420 * The contents need to actually be read from the ring buffer
4421 * for this function to be effective.
4422 */
4423 for (i = 0; i < DMUB_RB_CMD_SIZE / sizeof(uint64_t); i++)
4424 (void)READ_ONCE(*data++);
4425
4426 rptr += DMUB_RB_CMD_SIZE;
4427 if (rptr >= rb->capacity)
4428 rptr %= rb->capacity;
4429 }
4430 }
4431
4432 /**
4433 * @brief Initializes a DMCUB ringbuffer
4434 *
4435 * @param rb DMUB ringbuffer
4436 * @param init_params initial configuration for the ringbuffer
4437 */
dmub_rb_init(struct dmub_rb * rb,struct dmub_rb_init_params * init_params)4438 static inline void dmub_rb_init(struct dmub_rb *rb,
4439 struct dmub_rb_init_params *init_params)
4440 {
4441 rb->base_address = init_params->base_address;
4442 rb->capacity = init_params->capacity;
4443 rb->rptr = init_params->read_ptr;
4444 rb->wrpt = init_params->write_ptr;
4445 }
4446
4447 /**
4448 * @brief Copies output data from in/out commands into the given command.
4449 *
4450 * @param rb DMUB ringbuffer
4451 * @param cmd Command to copy data into
4452 */
dmub_rb_get_return_data(struct dmub_rb * rb,union dmub_rb_cmd * cmd)4453 static inline void dmub_rb_get_return_data(struct dmub_rb *rb,
4454 union dmub_rb_cmd *cmd)
4455 {
4456 // Copy rb entry back into command
4457 uint8_t *rd_ptr = (rb->rptr == 0) ?
4458 (uint8_t *)rb->base_address + rb->capacity - DMUB_RB_CMD_SIZE :
4459 (uint8_t *)rb->base_address + rb->rptr - DMUB_RB_CMD_SIZE;
4460
4461 dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE);
4462 }
4463
4464 #if defined(__cplusplus)
4465 }
4466 #endif
4467
4468 //==============================================================================
4469 //</DMUB_RB>====================================================================
4470 //==============================================================================
4471
4472 #endif /* _DMUB_CMD_H_ */
4473
