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Searched refs:dcore_offset (Results 1 – 3 of 3) sorted by relevance

/Linux-v6.6/drivers/accel/habanalabs/common/
Dsecurity.c292 u32 dcore_offset, u32 num_instances, u32 instance_offset, in hl_init_pb_with_mask() argument
318 i * dcore_offset + j * instance_offset, in hl_init_pb_with_mask()
343 int hl_init_pb(struct hl_device *hdev, u32 num_dcores, u32 dcore_offset, in hl_init_pb() argument
348 return hl_init_pb_with_mask(hdev, num_dcores, dcore_offset, in hl_init_pb()
372 u32 dcore_offset, u32 num_instances, u32 instance_offset, in hl_init_pb_ranges_with_mask() argument
402 i * dcore_offset + j * instance_offset, in hl_init_pb_ranges_with_mask()
430 u32 dcore_offset, u32 num_instances, u32 instance_offset, in hl_init_pb_ranges() argument
435 return hl_init_pb_ranges_with_mask(hdev, num_dcores, dcore_offset, in hl_init_pb_ranges()
455 int hl_init_pb_single_dcore(struct hl_device *hdev, u32 dcore_offset, in hl_init_pb_single_dcore() argument
478 dcore_offset + i * instance_offset, in hl_init_pb_single_dcore()
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Dhabanalabs.h4074 u32 dcore_offset, u32 num_instances, u32 instance_offset,
4077 int hl_init_pb(struct hl_device *hdev, u32 num_dcores, u32 dcore_offset,
4082 u32 dcore_offset, u32 num_instances, u32 instance_offset,
4087 u32 dcore_offset, u32 num_instances, u32 instance_offset,
4091 int hl_init_pb_single_dcore(struct hl_device *hdev, u32 dcore_offset,
4095 int hl_init_pb_ranges_single_dcore(struct hl_device *hdev, u32 dcore_offset,
4100 void hl_ack_pb(struct hl_device *hdev, u32 num_dcores, u32 dcore_offset,
4104 u32 dcore_offset, u32 num_instances, u32 instance_offset,
4106 void hl_ack_pb_single_dcore(struct hl_device *hdev, u32 dcore_offset,
/Linux-v6.6/drivers/accel/habanalabs/gaudi2/
Dgaudi2.c7452 u32 dcore_offset = dcore_id * DCORE_OFFSET; in gaudi2_mmu_dcore_prepare() local
7459 WREG32(mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_MMU_BP + dcore_offset, 0); in gaudi2_mmu_dcore_prepare()
7460 WREG32(mmDCORE0_EDMA0_QM_AXUSER_NONSECURED_HB_ASID + dcore_offset, rw_asid); in gaudi2_mmu_dcore_prepare()
7461 WREG32(mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_MMU_BP + dcore_offset, 0); in gaudi2_mmu_dcore_prepare()
7462 WREG32(mmDCORE0_EDMA0_CORE_CTX_AXUSER_HB_ASID + dcore_offset, rw_asid); in gaudi2_mmu_dcore_prepare()
7466 WREG32(mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_MMU_BP + dcore_offset, 0); in gaudi2_mmu_dcore_prepare()
7467 WREG32(mmDCORE0_EDMA1_QM_AXUSER_NONSECURED_HB_ASID + dcore_offset, rw_asid); in gaudi2_mmu_dcore_prepare()
7468 WREG32(mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_ASID + dcore_offset, rw_asid); in gaudi2_mmu_dcore_prepare()
7469 WREG32(mmDCORE0_EDMA1_CORE_CTX_AXUSER_HB_MMU_BP + dcore_offset, 0); in gaudi2_mmu_dcore_prepare()
7473 WREG32(mmDCORE0_SYNC_MNGR_GLBL_ASID_NONE_SEC_PRIV + dcore_offset, asid); in gaudi2_mmu_dcore_prepare()
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