Searched refs:dcn3_15_soc (Results 1 – 1 of 1) sorted by relevance
265 static struct _vcs_dpi_soc_bounding_box_st dcn3_15_soc = { variable669 dcn3_15_soc.num_chans = bw_params->num_channels; in dcn315_update_bw_bounding_box()671 dcn3_15_soc.dram_channel_width_bytes = bw_params->dram_channel_width_bytes; in dcn315_update_bw_bounding_box()684 dcn3_15_soc.clock_limits[i].state = i; in dcn315_update_bw_bounding_box()687 dcn3_15_soc.clock_limits[i].dcfclk_mhz = clk_table->entries[i].dcfclk_mhz; in dcn315_update_bw_bounding_box()688 dcn3_15_soc.clock_limits[i].fabricclk_mhz = clk_table->entries[i].fclk_mhz; in dcn315_update_bw_bounding_box()689 dcn3_15_soc.clock_limits[i].socclk_mhz = clk_table->entries[i].socclk_mhz; in dcn315_update_bw_bounding_box()690 …dcn3_15_soc.clock_limits[i].dram_speed_mts = clk_table->entries[i].memclk_mhz * 2 * clk_table->ent… in dcn315_update_bw_bounding_box()693 dcn3_15_soc.clock_limits[i].dtbclk_mhz = clk_table->entries[i].dtbclk_mhz; in dcn315_update_bw_bounding_box()694 dcn3_15_soc.clock_limits[i].phyclk_d18_mhz = clk_table->entries[i].phyclk_d18_mhz; in dcn315_update_bw_bounding_box()[all …]
