Searched refs:dclk_table (Results 1 – 20 of 20) sorted by relevance
65 struct arcturus_single_dpm_table dclk_table; member
907 single_dpm_table = &(dpm_context->dpm_tables.dclk_table); in arcturus_print_clk_levels()
1049 dpm_table = &dpm_context->dpm_tables.dclk_table; in navi10_set_default_dpm_table()
1042 dpm_table = &dpm_context->dpm_tables.dclk_table; in sienna_cichlid_set_default_dpm_table()
65 struct aldebaran_single_dpm_table dclk_table; member
666 dpm_table = &dpm_context->dpm_tables.dclk_table; in smu_v13_0_7_set_default_dpm_table()898 dpm_table = &dpm_context->dpm_tables.dclk_table; in smu_v13_0_7_get_dpm_ultimate_freq()1177 single_dpm_table = &(dpm_context->dpm_tables.dclk_table); in smu_v13_0_7_print_clk_levels()1596 single_dpm_table = &(dpm_context->dpm_tables.dclk_table); in smu_v13_0_7_force_clk_levels()1841 struct smu_13_0_dpm_table *dclk_table = in smu_v13_0_7_populate_umd_state_clk() local1842 &dpm_context->dpm_tables.dclk_table; in smu_v13_0_7_populate_umd_state_clk()1868 pstate_table->dclk_pstate.min = dclk_table->min; in smu_v13_0_7_populate_umd_state_clk()1869 pstate_table->dclk_pstate.peak = dclk_table->max; in smu_v13_0_7_populate_umd_state_clk()1882 pstate_table->dclk_pstate.standard = dclk_table->min; in smu_v13_0_7_populate_umd_state_clk()
677 dpm_table = &dpm_context->dpm_tables.dclk_table; in smu_v13_0_0_set_default_dpm_table()918 dpm_table = &dpm_context->dpm_tables.dclk_table; in smu_v13_0_0_get_dpm_ultimate_freq()1197 single_dpm_table = &(dpm_context->dpm_tables.dclk_table); in smu_v13_0_0_print_clk_levels()1616 single_dpm_table = &(dpm_context->dpm_tables.dclk_table); in smu_v13_0_0_force_clk_levels()1866 struct smu_13_0_dpm_table *dclk_table = in smu_v13_0_0_populate_umd_state_clk() local1867 &dpm_context->dpm_tables.dclk_table; in smu_v13_0_0_populate_umd_state_clk()1893 pstate_table->dclk_pstate.min = dclk_table->min; in smu_v13_0_0_populate_umd_state_clk()1894 pstate_table->dclk_pstate.peak = dclk_table->max; in smu_v13_0_0_populate_umd_state_clk()1907 pstate_table->dclk_pstate.standard = dclk_table->min; in smu_v13_0_0_populate_umd_state_clk()
1703 struct smu_13_0_dpm_table *dclk_table = in smu_v13_0_set_performance_level() local1704 &dpm_context->dpm_tables.dclk_table; in smu_v13_0_set_performance_level()1724 dclk_min = dclk_max = dclk_table->max; in smu_v13_0_set_performance_level()1732 dclk_min = dclk_max = dclk_table->min; in smu_v13_0_set_performance_level()1744 dclk_min = dclk_table->min; in smu_v13_0_set_performance_level()1745 dclk_max = dclk_table->max; in smu_v13_0_set_performance_level()
506 &dpm_context->dpm_tables.dclk_table, in smu_v13_0_6_set_default_dpm_table()977 single_dpm_table = &(dpm_context->dpm_tables.dclk_table); in smu_v13_0_6_print_clk_levels()
910 single_dpm_table = &(dpm_context->dpm_tables.dclk_table); in aldebaran_print_clk_levels()
82 static const struct ast_vbios_dclk_info dclk_table[] = { variable
472 clk_info = &dclk_table[vbios_mode->enh_table->dclk_index]; in ast_set_dclk_reg()
108 struct smu_11_0_dpm_table dclk_table; member
97 struct smu_13_0_dpm_table dclk_table; member
152 struct vega10_single_dpm_table dclk_table; member
130 struct vega12_single_dpm_table dclk_table; member
183 struct vega20_single_dpm_table dclk_table; member
709 dpm_table = &(data->dpm_table.dclk_table); in vega12_setup_default_dpm_tables()1193 min_freq = data->dpm_table.dclk_table.dpm_state.soft_min_level; in vega12_upload_dpm_min_level()1278 max_freq = data->dpm_table.dclk_table.dpm_state.soft_max_level; in vega12_upload_dpm_max_level()2449 dpm_table = &(data->dpm_table.dclk_table); in vega12_apply_clocks_adjust_rules()
695 dpm_table = &(data->dpm_table.dclk_table); in vega20_setup_default_dpm_tables()1849 min_freq = data->dpm_table.dclk_table.dpm_state.soft_min_level; in vega20_upload_dpm_min_level()1952 max_freq = data->dpm_table.dclk_table.dpm_state.soft_max_level; in vega20_upload_dpm_max_level()3846 dpm_table = &(data->dpm_table.dclk_table); in vega20_apply_clocks_adjust_rules()
1385 data->dpm_table.dclk_table.count = 0; in vega10_setup_default_dpm_tables()1399 dpm_table = &(data->dpm_table.dclk_table); in vega10_setup_default_dpm_tables()2075 &(data->dpm_table.dclk_table); in vega10_populate_smc_uvd_levels()
