Searched refs:dcefclk (Results 1 – 7 of 7) sorted by relevance
345 smu->smu_table.boot_values.dcefclk = 0; in smu_v12_0_get_vbios_bootup_values()362 smu->smu_table.boot_values.dcefclk = 0; in smu_v12_0_get_vbios_bootup_values()383 &smu->smu_table.boot_values.dcefclk); in smu_v12_0_get_vbios_bootup_values()
608 smu->smu_table.boot_values.dcefclk = 0; in smu_v13_0_get_vbios_bootup_values()622 smu->smu_table.boot_values.dcefclk = 0; in smu_v13_0_get_vbios_bootup_values()637 smu->smu_table.boot_values.dcefclk = 0; in smu_v13_0_get_vbios_bootup_values()668 smu->smu_table.boot_values.dcefclk = smu_info_v4_0->bootup_dcefclk_10khz; in smu_v13_0_get_vbios_bootup_values()892 max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100; in smu_v13_0_init_max_sustainable_clocks()
557 smu->smu_table.boot_values.dcefclk = 0; in smu_v11_0_get_vbios_bootup_values()574 smu->smu_table.boot_values.dcefclk = 0; in smu_v11_0_get_vbios_bootup_values()595 &smu->smu_table.boot_values.dcefclk); in smu_v11_0_get_vbios_bootup_values()838 max_sustainable_clocks->dcef_clock = smu->smu_table.boot_values.dcefclk / 100; in smu_v11_0_init_max_sustainable_clocks()
1078 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; in navi10_set_default_dpm_table()1096 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; in navi10_set_default_dpm_table()1114 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; in navi10_set_default_dpm_table()1132 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; in navi10_set_default_dpm_table()
1072 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; in sienna_cichlid_set_default_dpm_table()1090 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; in sienna_cichlid_set_default_dpm_table()1108 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; in sienna_cichlid_set_default_dpm_table()1126 dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.dcefclk / 100; in sienna_cichlid_set_default_dpm_table()
286 uint32_t dcefclk; member
1418 smu->smu_table.boot_values.dcefclk / 100); in smu_smc_hw_setup()
