1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright(c) 2020-2021 Intel Corporation. */
3 #ifndef __CXL_MEM_H__
4 #define __CXL_MEM_H__
5 #include <uapi/linux/cxl_mem.h>
6 #include <linux/cdev.h>
7 #include <linux/uuid.h>
8 #include <linux/rcuwait.h>
9 #include "cxl.h"
10
11 /* CXL 2.0 8.2.8.5.1.1 Memory Device Status Register */
12 #define CXLMDEV_STATUS_OFFSET 0x0
13 #define CXLMDEV_DEV_FATAL BIT(0)
14 #define CXLMDEV_FW_HALT BIT(1)
15 #define CXLMDEV_STATUS_MEDIA_STATUS_MASK GENMASK(3, 2)
16 #define CXLMDEV_MS_NOT_READY 0
17 #define CXLMDEV_MS_READY 1
18 #define CXLMDEV_MS_ERROR 2
19 #define CXLMDEV_MS_DISABLED 3
20 #define CXLMDEV_READY(status) \
21 (FIELD_GET(CXLMDEV_STATUS_MEDIA_STATUS_MASK, status) == \
22 CXLMDEV_MS_READY)
23 #define CXLMDEV_MBOX_IF_READY BIT(4)
24 #define CXLMDEV_RESET_NEEDED_MASK GENMASK(7, 5)
25 #define CXLMDEV_RESET_NEEDED_NOT 0
26 #define CXLMDEV_RESET_NEEDED_COLD 1
27 #define CXLMDEV_RESET_NEEDED_WARM 2
28 #define CXLMDEV_RESET_NEEDED_HOT 3
29 #define CXLMDEV_RESET_NEEDED_CXL 4
30 #define CXLMDEV_RESET_NEEDED(status) \
31 (FIELD_GET(CXLMDEV_RESET_NEEDED_MASK, status) != \
32 CXLMDEV_RESET_NEEDED_NOT)
33
34 /**
35 * struct cxl_memdev - CXL bus object representing a Type-3 Memory Device
36 * @dev: driver core device object
37 * @cdev: char dev core object for ioctl operations
38 * @cxlds: The device state backing this device
39 * @detach_work: active memdev lost a port in its ancestry
40 * @cxl_nvb: coordinate removal of @cxl_nvd if present
41 * @cxl_nvd: optional bridge to an nvdimm if the device supports pmem
42 * @endpoint: connection to the CXL port topology for this memory device
43 * @id: id number of this memdev instance.
44 * @depth: endpoint port depth
45 */
46 struct cxl_memdev {
47 struct device dev;
48 struct cdev cdev;
49 struct cxl_dev_state *cxlds;
50 struct work_struct detach_work;
51 struct cxl_nvdimm_bridge *cxl_nvb;
52 struct cxl_nvdimm *cxl_nvd;
53 struct cxl_port *endpoint;
54 int id;
55 int depth;
56 };
57
to_cxl_memdev(struct device * dev)58 static inline struct cxl_memdev *to_cxl_memdev(struct device *dev)
59 {
60 return container_of(dev, struct cxl_memdev, dev);
61 }
62
cxled_to_port(struct cxl_endpoint_decoder * cxled)63 static inline struct cxl_port *cxled_to_port(struct cxl_endpoint_decoder *cxled)
64 {
65 return to_cxl_port(cxled->cxld.dev.parent);
66 }
67
cxlrd_to_port(struct cxl_root_decoder * cxlrd)68 static inline struct cxl_port *cxlrd_to_port(struct cxl_root_decoder *cxlrd)
69 {
70 return to_cxl_port(cxlrd->cxlsd.cxld.dev.parent);
71 }
72
73 static inline struct cxl_memdev *
cxled_to_memdev(struct cxl_endpoint_decoder * cxled)74 cxled_to_memdev(struct cxl_endpoint_decoder *cxled)
75 {
76 struct cxl_port *port = to_cxl_port(cxled->cxld.dev.parent);
77
78 return to_cxl_memdev(port->uport_dev);
79 }
80
81 bool is_cxl_memdev(const struct device *dev);
is_cxl_endpoint(struct cxl_port * port)82 static inline bool is_cxl_endpoint(struct cxl_port *port)
83 {
84 return is_cxl_memdev(port->uport_dev);
85 }
86
87 struct cxl_memdev *devm_cxl_add_memdev(struct cxl_dev_state *cxlds);
88 struct cxl_memdev_state;
89 int cxl_memdev_setup_fw_upload(struct cxl_memdev_state *mds);
90 int devm_cxl_dpa_reserve(struct cxl_endpoint_decoder *cxled,
91 resource_size_t base, resource_size_t len,
92 resource_size_t skipped);
93
cxl_ep_load(struct cxl_port * port,struct cxl_memdev * cxlmd)94 static inline struct cxl_ep *cxl_ep_load(struct cxl_port *port,
95 struct cxl_memdev *cxlmd)
96 {
97 if (!port)
98 return NULL;
99
100 return xa_load(&port->endpoints, (unsigned long)&cxlmd->dev);
101 }
102
103 /**
104 * struct cxl_mbox_cmd - A command to be submitted to hardware.
105 * @opcode: (input) The command set and command submitted to hardware.
106 * @payload_in: (input) Pointer to the input payload.
107 * @payload_out: (output) Pointer to the output payload. Must be allocated by
108 * the caller.
109 * @size_in: (input) Number of bytes to load from @payload_in.
110 * @size_out: (input) Max number of bytes loaded into @payload_out.
111 * (output) Number of bytes generated by the device. For fixed size
112 * outputs commands this is always expected to be deterministic. For
113 * variable sized output commands, it tells the exact number of bytes
114 * written.
115 * @min_out: (input) internal command output payload size validation
116 * @poll_count: (input) Number of timeouts to attempt.
117 * @poll_interval_ms: (input) Time between mailbox background command polling
118 * interval timeouts.
119 * @return_code: (output) Error code returned from hardware.
120 *
121 * This is the primary mechanism used to send commands to the hardware.
122 * All the fields except @payload_* correspond exactly to the fields described in
123 * Command Register section of the CXL 2.0 8.2.8.4.5. @payload_in and
124 * @payload_out are written to, and read from the Command Payload Registers
125 * defined in CXL 2.0 8.2.8.4.8.
126 */
127 struct cxl_mbox_cmd {
128 u16 opcode;
129 void *payload_in;
130 void *payload_out;
131 size_t size_in;
132 size_t size_out;
133 size_t min_out;
134 int poll_count;
135 int poll_interval_ms;
136 u16 return_code;
137 };
138
139 /*
140 * Per CXL 3.0 Section 8.2.8.4.5.1
141 */
142 #define CMD_CMD_RC_TABLE \
143 C(SUCCESS, 0, NULL), \
144 C(BACKGROUND, -ENXIO, "background cmd started successfully"), \
145 C(INPUT, -ENXIO, "cmd input was invalid"), \
146 C(UNSUPPORTED, -ENXIO, "cmd is not supported"), \
147 C(INTERNAL, -ENXIO, "internal device error"), \
148 C(RETRY, -ENXIO, "temporary error, retry once"), \
149 C(BUSY, -ENXIO, "ongoing background operation"), \
150 C(MEDIADISABLED, -ENXIO, "media access is disabled"), \
151 C(FWINPROGRESS, -ENXIO, "one FW package can be transferred at a time"), \
152 C(FWOOO, -ENXIO, "FW package content was transferred out of order"), \
153 C(FWAUTH, -ENXIO, "FW package authentication failed"), \
154 C(FWSLOT, -ENXIO, "FW slot is not supported for requested operation"), \
155 C(FWROLLBACK, -ENXIO, "rolled back to the previous active FW"), \
156 C(FWRESET, -ENXIO, "FW failed to activate, needs cold reset"), \
157 C(HANDLE, -ENXIO, "one or more Event Record Handles were invalid"), \
158 C(PADDR, -EFAULT, "physical address specified is invalid"), \
159 C(POISONLMT, -ENXIO, "poison injection limit has been reached"), \
160 C(MEDIAFAILURE, -ENXIO, "permanent issue with the media"), \
161 C(ABORT, -ENXIO, "background cmd was aborted by device"), \
162 C(SECURITY, -ENXIO, "not valid in the current security state"), \
163 C(PASSPHRASE, -ENXIO, "phrase doesn't match current set passphrase"), \
164 C(MBUNSUPPORTED, -ENXIO, "unsupported on the mailbox it was issued on"),\
165 C(PAYLOADLEN, -ENXIO, "invalid payload length"), \
166 C(LOG, -ENXIO, "invalid or unsupported log page"), \
167 C(INTERRUPTED, -ENXIO, "asynchronous event occured"), \
168 C(FEATUREVERSION, -ENXIO, "unsupported feature version"), \
169 C(FEATURESELVALUE, -ENXIO, "unsupported feature selection value"), \
170 C(FEATURETRANSFERIP, -ENXIO, "feature transfer in progress"), \
171 C(FEATURETRANSFEROOO, -ENXIO, "feature transfer out of order"), \
172 C(RESOURCEEXHAUSTED, -ENXIO, "resources are exhausted"), \
173 C(EXTLIST, -ENXIO, "invalid Extent List"), \
174
175 #undef C
176 #define C(a, b, c) CXL_MBOX_CMD_RC_##a
177 enum { CMD_CMD_RC_TABLE };
178 #undef C
179 #define C(a, b, c) { b, c }
180 struct cxl_mbox_cmd_rc {
181 int err;
182 const char *desc;
183 };
184
185 static const
186 struct cxl_mbox_cmd_rc cxl_mbox_cmd_rctable[] ={ CMD_CMD_RC_TABLE };
187 #undef C
188
cxl_mbox_cmd_rc2str(struct cxl_mbox_cmd * mbox_cmd)189 static inline const char *cxl_mbox_cmd_rc2str(struct cxl_mbox_cmd *mbox_cmd)
190 {
191 return cxl_mbox_cmd_rctable[mbox_cmd->return_code].desc;
192 }
193
cxl_mbox_cmd_rc2errno(struct cxl_mbox_cmd * mbox_cmd)194 static inline int cxl_mbox_cmd_rc2errno(struct cxl_mbox_cmd *mbox_cmd)
195 {
196 return cxl_mbox_cmd_rctable[mbox_cmd->return_code].err;
197 }
198
199 /*
200 * CXL 2.0 - Memory capacity multiplier
201 * See Section 8.2.9.5
202 *
203 * Volatile, Persistent, and Partition capacities are specified to be in
204 * multiples of 256MB - define a multiplier to convert to/from bytes.
205 */
206 #define CXL_CAPACITY_MULTIPLIER SZ_256M
207
208 /*
209 * Event Interrupt Policy
210 *
211 * CXL rev 3.0 section 8.2.9.2.4; Table 8-52
212 */
213 enum cxl_event_int_mode {
214 CXL_INT_NONE = 0x00,
215 CXL_INT_MSI_MSIX = 0x01,
216 CXL_INT_FW = 0x02
217 };
218 struct cxl_event_interrupt_policy {
219 u8 info_settings;
220 u8 warn_settings;
221 u8 failure_settings;
222 u8 fatal_settings;
223 } __packed;
224
225 /**
226 * struct cxl_event_state - Event log driver state
227 *
228 * @buf: Buffer to receive event data
229 * @log_lock: Serialize event_buf and log use
230 */
231 struct cxl_event_state {
232 struct cxl_get_event_payload *buf;
233 struct mutex log_lock;
234 };
235
236 /* Device enabled poison commands */
237 enum poison_cmd_enabled_bits {
238 CXL_POISON_ENABLED_LIST,
239 CXL_POISON_ENABLED_INJECT,
240 CXL_POISON_ENABLED_CLEAR,
241 CXL_POISON_ENABLED_SCAN_CAPS,
242 CXL_POISON_ENABLED_SCAN_MEDIA,
243 CXL_POISON_ENABLED_SCAN_RESULTS,
244 CXL_POISON_ENABLED_MAX
245 };
246
247 /* Device enabled security commands */
248 enum security_cmd_enabled_bits {
249 CXL_SEC_ENABLED_SANITIZE,
250 CXL_SEC_ENABLED_SECURE_ERASE,
251 CXL_SEC_ENABLED_GET_SECURITY_STATE,
252 CXL_SEC_ENABLED_SET_PASSPHRASE,
253 CXL_SEC_ENABLED_DISABLE_PASSPHRASE,
254 CXL_SEC_ENABLED_UNLOCK,
255 CXL_SEC_ENABLED_FREEZE_SECURITY,
256 CXL_SEC_ENABLED_PASSPHRASE_SECURE_ERASE,
257 CXL_SEC_ENABLED_MAX
258 };
259
260 /**
261 * struct cxl_poison_state - Driver poison state info
262 *
263 * @max_errors: Maximum media error records held in device cache
264 * @enabled_cmds: All poison commands enabled in the CEL
265 * @list_out: The poison list payload returned by device
266 * @lock: Protect reads of the poison list
267 *
268 * Reads of the poison list are synchronized to ensure that a reader
269 * does not get an incomplete list because their request overlapped
270 * (was interrupted or preceded by) another read request of the same
271 * DPA range. CXL Spec 3.0 Section 8.2.9.8.4.1
272 */
273 struct cxl_poison_state {
274 u32 max_errors;
275 DECLARE_BITMAP(enabled_cmds, CXL_POISON_ENABLED_MAX);
276 struct cxl_mbox_poison_out *list_out;
277 struct mutex lock; /* Protect reads of poison list */
278 };
279
280 /*
281 * Get FW Info
282 * CXL rev 3.0 section 8.2.9.3.1; Table 8-56
283 */
284 struct cxl_mbox_get_fw_info {
285 u8 num_slots;
286 u8 slot_info;
287 u8 activation_cap;
288 u8 reserved[13];
289 char slot_1_revision[16];
290 char slot_2_revision[16];
291 char slot_3_revision[16];
292 char slot_4_revision[16];
293 } __packed;
294
295 #define CXL_FW_INFO_SLOT_INFO_CUR_MASK GENMASK(2, 0)
296 #define CXL_FW_INFO_SLOT_INFO_NEXT_MASK GENMASK(5, 3)
297 #define CXL_FW_INFO_SLOT_INFO_NEXT_SHIFT 3
298 #define CXL_FW_INFO_ACTIVATION_CAP_HAS_LIVE_ACTIVATE BIT(0)
299
300 /*
301 * Transfer FW Input Payload
302 * CXL rev 3.0 section 8.2.9.3.2; Table 8-57
303 */
304 struct cxl_mbox_transfer_fw {
305 u8 action;
306 u8 slot;
307 u8 reserved[2];
308 __le32 offset;
309 u8 reserved2[0x78];
310 u8 data[];
311 } __packed;
312
313 #define CXL_FW_TRANSFER_ACTION_FULL 0x0
314 #define CXL_FW_TRANSFER_ACTION_INITIATE 0x1
315 #define CXL_FW_TRANSFER_ACTION_CONTINUE 0x2
316 #define CXL_FW_TRANSFER_ACTION_END 0x3
317 #define CXL_FW_TRANSFER_ACTION_ABORT 0x4
318
319 /*
320 * CXL rev 3.0 section 8.2.9.3.2 mandates 128-byte alignment for FW packages
321 * and for each part transferred in a Transfer FW command.
322 */
323 #define CXL_FW_TRANSFER_ALIGNMENT 128
324
325 /*
326 * Activate FW Input Payload
327 * CXL rev 3.0 section 8.2.9.3.3; Table 8-58
328 */
329 struct cxl_mbox_activate_fw {
330 u8 action;
331 u8 slot;
332 } __packed;
333
334 #define CXL_FW_ACTIVATE_ONLINE 0x0
335 #define CXL_FW_ACTIVATE_OFFLINE 0x1
336
337 /* FW state bits */
338 #define CXL_FW_STATE_BITS 32
339 #define CXL_FW_CANCEL 0
340
341 /**
342 * struct cxl_fw_state - Firmware upload / activation state
343 *
344 * @state: fw_uploader state bitmask
345 * @oneshot: whether the fw upload fits in a single transfer
346 * @num_slots: Number of FW slots available
347 * @cur_slot: Slot number currently active
348 * @next_slot: Slot number for the new firmware
349 */
350 struct cxl_fw_state {
351 DECLARE_BITMAP(state, CXL_FW_STATE_BITS);
352 bool oneshot;
353 int num_slots;
354 int cur_slot;
355 int next_slot;
356 };
357
358 /**
359 * struct cxl_security_state - Device security state
360 *
361 * @state: state of last security operation
362 * @enabled_cmds: All security commands enabled in the CEL
363 * @poll: polling for sanitization is enabled, device has no mbox irq support
364 * @poll_tmo_secs: polling timeout
365 * @poll_dwork: polling work item
366 * @sanitize_node: sanitation sysfs file to notify
367 */
368 struct cxl_security_state {
369 unsigned long state;
370 DECLARE_BITMAP(enabled_cmds, CXL_SEC_ENABLED_MAX);
371 bool poll;
372 int poll_tmo_secs;
373 struct delayed_work poll_dwork;
374 struct kernfs_node *sanitize_node;
375 };
376
377 /*
378 * enum cxl_devtype - delineate type-2 from a generic type-3 device
379 * @CXL_DEVTYPE_DEVMEM - Vendor specific CXL Type-2 device implementing HDM-D or
380 * HDM-DB, no requirement that this device implements a
381 * mailbox, or other memory-device-standard manageability
382 * flows.
383 * @CXL_DEVTYPE_CLASSMEM - Common class definition of a CXL Type-3 device with
384 * HDM-H and class-mandatory memory device registers
385 */
386 enum cxl_devtype {
387 CXL_DEVTYPE_DEVMEM,
388 CXL_DEVTYPE_CLASSMEM,
389 };
390
391 /**
392 * struct cxl_dev_state - The driver device state
393 *
394 * cxl_dev_state represents the CXL driver/device state. It provides an
395 * interface to mailbox commands as well as some cached data about the device.
396 * Currently only memory devices are represented.
397 *
398 * @dev: The device associated with this CXL state
399 * @cxlmd: The device representing the CXL.mem capabilities of @dev
400 * @regs: Parsed register blocks
401 * @cxl_dvsec: Offset to the PCIe device DVSEC
402 * @rcd: operating in RCD mode (CXL 3.0 9.11.8 CXL Devices Attached to an RCH)
403 * @media_ready: Indicate whether the device media is usable
404 * @dpa_res: Overall DPA resource tree for the device
405 * @pmem_res: Active Persistent memory capacity configuration
406 * @ram_res: Active Volatile memory capacity configuration
407 * @component_reg_phys: register base of component registers
408 * @serial: PCIe Device Serial Number
409 * @type: Generic Memory Class device or Vendor Specific Memory device
410 */
411 struct cxl_dev_state {
412 struct device *dev;
413 struct cxl_memdev *cxlmd;
414 struct cxl_regs regs;
415 int cxl_dvsec;
416 bool rcd;
417 bool media_ready;
418 struct resource dpa_res;
419 struct resource pmem_res;
420 struct resource ram_res;
421 resource_size_t component_reg_phys;
422 u64 serial;
423 enum cxl_devtype type;
424 };
425
426 /**
427 * struct cxl_memdev_state - Generic Type-3 Memory Device Class driver data
428 *
429 * CXL 8.1.12.1 PCI Header - Class Code Register Memory Device defines
430 * common memory device functionality like the presence of a mailbox and
431 * the functionality related to that like Identify Memory Device and Get
432 * Partition Info
433 * @cxlds: Core driver state common across Type-2 and Type-3 devices
434 * @payload_size: Size of space for payload
435 * (CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register)
436 * @lsa_size: Size of Label Storage Area
437 * (CXL 2.0 8.2.9.5.1.1 Identify Memory Device)
438 * @mbox_mutex: Mutex to synchronize mailbox access.
439 * @firmware_version: Firmware version for the memory device.
440 * @enabled_cmds: Hardware commands found enabled in CEL.
441 * @exclusive_cmds: Commands that are kernel-internal only
442 * @total_bytes: sum of all possible capacities
443 * @volatile_only_bytes: hard volatile capacity
444 * @persistent_only_bytes: hard persistent capacity
445 * @partition_align_bytes: alignment size for partition-able capacity
446 * @active_volatile_bytes: sum of hard + soft volatile
447 * @active_persistent_bytes: sum of hard + soft persistent
448 * @next_volatile_bytes: volatile capacity change pending device reset
449 * @next_persistent_bytes: persistent capacity change pending device reset
450 * @event: event log driver state
451 * @poison: poison driver state info
452 * @security: security driver state info
453 * @fw: firmware upload / activation state
454 * @mbox_send: @dev specific transport for transmitting mailbox commands
455 *
456 * See CXL 3.0 8.2.9.8.2 Capacity Configuration and Label Storage for
457 * details on capacity parameters.
458 */
459 struct cxl_memdev_state {
460 struct cxl_dev_state cxlds;
461 size_t payload_size;
462 size_t lsa_size;
463 struct mutex mbox_mutex; /* Protects device mailbox and firmware */
464 char firmware_version[0x10];
465 DECLARE_BITMAP(enabled_cmds, CXL_MEM_COMMAND_ID_MAX);
466 DECLARE_BITMAP(exclusive_cmds, CXL_MEM_COMMAND_ID_MAX);
467 u64 total_bytes;
468 u64 volatile_only_bytes;
469 u64 persistent_only_bytes;
470 u64 partition_align_bytes;
471 u64 active_volatile_bytes;
472 u64 active_persistent_bytes;
473 u64 next_volatile_bytes;
474 u64 next_persistent_bytes;
475 struct cxl_event_state event;
476 struct cxl_poison_state poison;
477 struct cxl_security_state security;
478 struct cxl_fw_state fw;
479
480 struct rcuwait mbox_wait;
481 int (*mbox_send)(struct cxl_memdev_state *mds,
482 struct cxl_mbox_cmd *cmd);
483 };
484
485 static inline struct cxl_memdev_state *
to_cxl_memdev_state(struct cxl_dev_state * cxlds)486 to_cxl_memdev_state(struct cxl_dev_state *cxlds)
487 {
488 if (cxlds->type != CXL_DEVTYPE_CLASSMEM)
489 return NULL;
490 return container_of(cxlds, struct cxl_memdev_state, cxlds);
491 }
492
493 enum cxl_opcode {
494 CXL_MBOX_OP_INVALID = 0x0000,
495 CXL_MBOX_OP_RAW = CXL_MBOX_OP_INVALID,
496 CXL_MBOX_OP_GET_EVENT_RECORD = 0x0100,
497 CXL_MBOX_OP_CLEAR_EVENT_RECORD = 0x0101,
498 CXL_MBOX_OP_GET_EVT_INT_POLICY = 0x0102,
499 CXL_MBOX_OP_SET_EVT_INT_POLICY = 0x0103,
500 CXL_MBOX_OP_GET_FW_INFO = 0x0200,
501 CXL_MBOX_OP_TRANSFER_FW = 0x0201,
502 CXL_MBOX_OP_ACTIVATE_FW = 0x0202,
503 CXL_MBOX_OP_SET_TIMESTAMP = 0x0301,
504 CXL_MBOX_OP_GET_SUPPORTED_LOGS = 0x0400,
505 CXL_MBOX_OP_GET_LOG = 0x0401,
506 CXL_MBOX_OP_IDENTIFY = 0x4000,
507 CXL_MBOX_OP_GET_PARTITION_INFO = 0x4100,
508 CXL_MBOX_OP_SET_PARTITION_INFO = 0x4101,
509 CXL_MBOX_OP_GET_LSA = 0x4102,
510 CXL_MBOX_OP_SET_LSA = 0x4103,
511 CXL_MBOX_OP_GET_HEALTH_INFO = 0x4200,
512 CXL_MBOX_OP_GET_ALERT_CONFIG = 0x4201,
513 CXL_MBOX_OP_SET_ALERT_CONFIG = 0x4202,
514 CXL_MBOX_OP_GET_SHUTDOWN_STATE = 0x4203,
515 CXL_MBOX_OP_SET_SHUTDOWN_STATE = 0x4204,
516 CXL_MBOX_OP_GET_POISON = 0x4300,
517 CXL_MBOX_OP_INJECT_POISON = 0x4301,
518 CXL_MBOX_OP_CLEAR_POISON = 0x4302,
519 CXL_MBOX_OP_GET_SCAN_MEDIA_CAPS = 0x4303,
520 CXL_MBOX_OP_SCAN_MEDIA = 0x4304,
521 CXL_MBOX_OP_GET_SCAN_MEDIA = 0x4305,
522 CXL_MBOX_OP_SANITIZE = 0x4400,
523 CXL_MBOX_OP_SECURE_ERASE = 0x4401,
524 CXL_MBOX_OP_GET_SECURITY_STATE = 0x4500,
525 CXL_MBOX_OP_SET_PASSPHRASE = 0x4501,
526 CXL_MBOX_OP_DISABLE_PASSPHRASE = 0x4502,
527 CXL_MBOX_OP_UNLOCK = 0x4503,
528 CXL_MBOX_OP_FREEZE_SECURITY = 0x4504,
529 CXL_MBOX_OP_PASSPHRASE_SECURE_ERASE = 0x4505,
530 CXL_MBOX_OP_MAX = 0x10000
531 };
532
533 #define DEFINE_CXL_CEL_UUID \
534 UUID_INIT(0xda9c0b5, 0xbf41, 0x4b78, 0x8f, 0x79, 0x96, 0xb1, 0x62, \
535 0x3b, 0x3f, 0x17)
536
537 #define DEFINE_CXL_VENDOR_DEBUG_UUID \
538 UUID_INIT(0xe1819d9, 0x11a9, 0x400c, 0x81, 0x1f, 0xd6, 0x07, 0x19, \
539 0x40, 0x3d, 0x86)
540
541 struct cxl_mbox_get_supported_logs {
542 __le16 entries;
543 u8 rsvd[6];
544 struct cxl_gsl_entry {
545 uuid_t uuid;
546 __le32 size;
547 } __packed entry[];
548 } __packed;
549
550 struct cxl_cel_entry {
551 __le16 opcode;
552 __le16 effect;
553 } __packed;
554
555 struct cxl_mbox_get_log {
556 uuid_t uuid;
557 __le32 offset;
558 __le32 length;
559 } __packed;
560
561 /* See CXL 2.0 Table 175 Identify Memory Device Output Payload */
562 struct cxl_mbox_identify {
563 char fw_revision[0x10];
564 __le64 total_capacity;
565 __le64 volatile_capacity;
566 __le64 persistent_capacity;
567 __le64 partition_align;
568 __le16 info_event_log_size;
569 __le16 warning_event_log_size;
570 __le16 failure_event_log_size;
571 __le16 fatal_event_log_size;
572 __le32 lsa_size;
573 u8 poison_list_max_mer[3];
574 __le16 inject_poison_limit;
575 u8 poison_caps;
576 u8 qos_telemetry_caps;
577 } __packed;
578
579 /*
580 * Common Event Record Format
581 * CXL rev 3.0 section 8.2.9.2.1; Table 8-42
582 */
583 struct cxl_event_record_hdr {
584 uuid_t id;
585 u8 length;
586 u8 flags[3];
587 __le16 handle;
588 __le16 related_handle;
589 __le64 timestamp;
590 u8 maint_op_class;
591 u8 reserved[15];
592 } __packed;
593
594 #define CXL_EVENT_RECORD_DATA_LENGTH 0x50
595 struct cxl_event_record_raw {
596 struct cxl_event_record_hdr hdr;
597 u8 data[CXL_EVENT_RECORD_DATA_LENGTH];
598 } __packed;
599
600 /*
601 * Get Event Records output payload
602 * CXL rev 3.0 section 8.2.9.2.2; Table 8-50
603 */
604 #define CXL_GET_EVENT_FLAG_OVERFLOW BIT(0)
605 #define CXL_GET_EVENT_FLAG_MORE_RECORDS BIT(1)
606 struct cxl_get_event_payload {
607 u8 flags;
608 u8 reserved1;
609 __le16 overflow_err_count;
610 __le64 first_overflow_timestamp;
611 __le64 last_overflow_timestamp;
612 __le16 record_count;
613 u8 reserved2[10];
614 struct cxl_event_record_raw records[];
615 } __packed;
616
617 /*
618 * CXL rev 3.0 section 8.2.9.2.2; Table 8-49
619 */
620 enum cxl_event_log_type {
621 CXL_EVENT_TYPE_INFO = 0x00,
622 CXL_EVENT_TYPE_WARN,
623 CXL_EVENT_TYPE_FAIL,
624 CXL_EVENT_TYPE_FATAL,
625 CXL_EVENT_TYPE_MAX
626 };
627
628 /*
629 * Clear Event Records input payload
630 * CXL rev 3.0 section 8.2.9.2.3; Table 8-51
631 */
632 struct cxl_mbox_clear_event_payload {
633 u8 event_log; /* enum cxl_event_log_type */
634 u8 clear_flags;
635 u8 nr_recs;
636 u8 reserved[3];
637 __le16 handles[];
638 } __packed;
639 #define CXL_CLEAR_EVENT_MAX_HANDLES U8_MAX
640
641 /*
642 * General Media Event Record
643 * CXL rev 3.0 Section 8.2.9.2.1.1; Table 8-43
644 */
645 #define CXL_EVENT_GEN_MED_COMP_ID_SIZE 0x10
646 struct cxl_event_gen_media {
647 struct cxl_event_record_hdr hdr;
648 __le64 phys_addr;
649 u8 descriptor;
650 u8 type;
651 u8 transaction_type;
652 u8 validity_flags[2];
653 u8 channel;
654 u8 rank;
655 u8 device[3];
656 u8 component_id[CXL_EVENT_GEN_MED_COMP_ID_SIZE];
657 u8 reserved[46];
658 } __packed;
659
660 /*
661 * DRAM Event Record - DER
662 * CXL rev 3.0 section 8.2.9.2.1.2; Table 3-44
663 */
664 #define CXL_EVENT_DER_CORRECTION_MASK_SIZE 0x20
665 struct cxl_event_dram {
666 struct cxl_event_record_hdr hdr;
667 __le64 phys_addr;
668 u8 descriptor;
669 u8 type;
670 u8 transaction_type;
671 u8 validity_flags[2];
672 u8 channel;
673 u8 rank;
674 u8 nibble_mask[3];
675 u8 bank_group;
676 u8 bank;
677 u8 row[3];
678 u8 column[2];
679 u8 correction_mask[CXL_EVENT_DER_CORRECTION_MASK_SIZE];
680 u8 reserved[0x17];
681 } __packed;
682
683 /*
684 * Get Health Info Record
685 * CXL rev 3.0 section 8.2.9.8.3.1; Table 8-100
686 */
687 struct cxl_get_health_info {
688 u8 health_status;
689 u8 media_status;
690 u8 add_status;
691 u8 life_used;
692 u8 device_temp[2];
693 u8 dirty_shutdown_cnt[4];
694 u8 cor_vol_err_cnt[4];
695 u8 cor_per_err_cnt[4];
696 } __packed;
697
698 /*
699 * Memory Module Event Record
700 * CXL rev 3.0 section 8.2.9.2.1.3; Table 8-45
701 */
702 struct cxl_event_mem_module {
703 struct cxl_event_record_hdr hdr;
704 u8 event_type;
705 struct cxl_get_health_info info;
706 u8 reserved[0x3d];
707 } __packed;
708
709 struct cxl_mbox_get_partition_info {
710 __le64 active_volatile_cap;
711 __le64 active_persistent_cap;
712 __le64 next_volatile_cap;
713 __le64 next_persistent_cap;
714 } __packed;
715
716 struct cxl_mbox_get_lsa {
717 __le32 offset;
718 __le32 length;
719 } __packed;
720
721 struct cxl_mbox_set_lsa {
722 __le32 offset;
723 __le32 reserved;
724 u8 data[];
725 } __packed;
726
727 struct cxl_mbox_set_partition_info {
728 __le64 volatile_capacity;
729 u8 flags;
730 } __packed;
731
732 #define CXL_SET_PARTITION_IMMEDIATE_FLAG BIT(0)
733
734 /* Set Timestamp CXL 3.0 Spec 8.2.9.4.2 */
735 struct cxl_mbox_set_timestamp_in {
736 __le64 timestamp;
737
738 } __packed;
739
740 /* Get Poison List CXL 3.0 Spec 8.2.9.8.4.1 */
741 struct cxl_mbox_poison_in {
742 __le64 offset;
743 __le64 length;
744 } __packed;
745
746 struct cxl_mbox_poison_out {
747 u8 flags;
748 u8 rsvd1;
749 __le64 overflow_ts;
750 __le16 count;
751 u8 rsvd2[20];
752 struct cxl_poison_record {
753 __le64 address;
754 __le32 length;
755 __le32 rsvd;
756 } __packed record[];
757 } __packed;
758
759 /*
760 * Get Poison List address field encodes the starting
761 * address of poison, and the source of the poison.
762 */
763 #define CXL_POISON_START_MASK GENMASK_ULL(63, 6)
764 #define CXL_POISON_SOURCE_MASK GENMASK(2, 0)
765
766 /* Get Poison List record length is in units of 64 bytes */
767 #define CXL_POISON_LEN_MULT 64
768
769 /* Kernel defined maximum for a list of poison errors */
770 #define CXL_POISON_LIST_MAX 1024
771
772 /* Get Poison List: Payload out flags */
773 #define CXL_POISON_FLAG_MORE BIT(0)
774 #define CXL_POISON_FLAG_OVERFLOW BIT(1)
775 #define CXL_POISON_FLAG_SCANNING BIT(2)
776
777 /* Get Poison List: Poison Source */
778 #define CXL_POISON_SOURCE_UNKNOWN 0
779 #define CXL_POISON_SOURCE_EXTERNAL 1
780 #define CXL_POISON_SOURCE_INTERNAL 2
781 #define CXL_POISON_SOURCE_INJECTED 3
782 #define CXL_POISON_SOURCE_VENDOR 7
783
784 /* Inject & Clear Poison CXL 3.0 Spec 8.2.9.8.4.2/3 */
785 struct cxl_mbox_inject_poison {
786 __le64 address;
787 };
788
789 /* Clear Poison CXL 3.0 Spec 8.2.9.8.4.3 */
790 struct cxl_mbox_clear_poison {
791 __le64 address;
792 u8 write_data[CXL_POISON_LEN_MULT];
793 } __packed;
794
795 /**
796 * struct cxl_mem_command - Driver representation of a memory device command
797 * @info: Command information as it exists for the UAPI
798 * @opcode: The actual bits used for the mailbox protocol
799 * @flags: Set of flags effecting driver behavior.
800 *
801 * * %CXL_CMD_FLAG_FORCE_ENABLE: In cases of error, commands with this flag
802 * will be enabled by the driver regardless of what hardware may have
803 * advertised.
804 *
805 * The cxl_mem_command is the driver's internal representation of commands that
806 * are supported by the driver. Some of these commands may not be supported by
807 * the hardware. The driver will use @info to validate the fields passed in by
808 * the user then submit the @opcode to the hardware.
809 *
810 * See struct cxl_command_info.
811 */
812 struct cxl_mem_command {
813 struct cxl_command_info info;
814 enum cxl_opcode opcode;
815 u32 flags;
816 #define CXL_CMD_FLAG_FORCE_ENABLE BIT(0)
817 };
818
819 #define CXL_PMEM_SEC_STATE_USER_PASS_SET 0x01
820 #define CXL_PMEM_SEC_STATE_MASTER_PASS_SET 0x02
821 #define CXL_PMEM_SEC_STATE_LOCKED 0x04
822 #define CXL_PMEM_SEC_STATE_FROZEN 0x08
823 #define CXL_PMEM_SEC_STATE_USER_PLIMIT 0x10
824 #define CXL_PMEM_SEC_STATE_MASTER_PLIMIT 0x20
825
826 /* set passphrase input payload */
827 struct cxl_set_pass {
828 u8 type;
829 u8 reserved[31];
830 /* CXL field using NVDIMM define, same length */
831 u8 old_pass[NVDIMM_PASSPHRASE_LEN];
832 u8 new_pass[NVDIMM_PASSPHRASE_LEN];
833 } __packed;
834
835 /* disable passphrase input payload */
836 struct cxl_disable_pass {
837 u8 type;
838 u8 reserved[31];
839 u8 pass[NVDIMM_PASSPHRASE_LEN];
840 } __packed;
841
842 /* passphrase secure erase payload */
843 struct cxl_pass_erase {
844 u8 type;
845 u8 reserved[31];
846 u8 pass[NVDIMM_PASSPHRASE_LEN];
847 } __packed;
848
849 enum {
850 CXL_PMEM_SEC_PASS_MASTER = 0,
851 CXL_PMEM_SEC_PASS_USER,
852 };
853
854 int cxl_internal_send_cmd(struct cxl_memdev_state *mds,
855 struct cxl_mbox_cmd *cmd);
856 int cxl_dev_state_identify(struct cxl_memdev_state *mds);
857 int cxl_await_media_ready(struct cxl_dev_state *cxlds);
858 int cxl_enumerate_cmds(struct cxl_memdev_state *mds);
859 int cxl_mem_create_range_info(struct cxl_memdev_state *mds);
860 struct cxl_memdev_state *cxl_memdev_state_create(struct device *dev);
861 void set_exclusive_cxl_commands(struct cxl_memdev_state *mds,
862 unsigned long *cmds);
863 void clear_exclusive_cxl_commands(struct cxl_memdev_state *mds,
864 unsigned long *cmds);
865 void cxl_mem_get_event_records(struct cxl_memdev_state *mds, u32 status);
866 int cxl_set_timestamp(struct cxl_memdev_state *mds);
867 int cxl_poison_state_init(struct cxl_memdev_state *mds);
868 int cxl_mem_get_poison(struct cxl_memdev *cxlmd, u64 offset, u64 len,
869 struct cxl_region *cxlr);
870 int cxl_trigger_poison_list(struct cxl_memdev *cxlmd);
871 int cxl_inject_poison(struct cxl_memdev *cxlmd, u64 dpa);
872 int cxl_clear_poison(struct cxl_memdev *cxlmd, u64 dpa);
873
874 #ifdef CONFIG_CXL_SUSPEND
875 void cxl_mem_active_inc(void);
876 void cxl_mem_active_dec(void);
877 #else
cxl_mem_active_inc(void)878 static inline void cxl_mem_active_inc(void)
879 {
880 }
cxl_mem_active_dec(void)881 static inline void cxl_mem_active_dec(void)
882 {
883 }
884 #endif
885
886 int cxl_mem_sanitize(struct cxl_memdev_state *mds, u16 cmd);
887
888 struct cxl_hdm {
889 struct cxl_component_regs regs;
890 unsigned int decoder_count;
891 unsigned int target_count;
892 unsigned int interleave_mask;
893 struct cxl_port *port;
894 };
895
896 struct seq_file;
897 struct dentry *cxl_debugfs_create_dir(const char *dir);
898 void cxl_dpa_debug(struct seq_file *file, struct cxl_dev_state *cxlds);
899 #endif /* __CXL_MEM_H__ */
900
